cvt_V1190.c

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00001 
00002 
00010 
00011 
00013 // File includes
00015 #include <memory.h>
00016 #include <string.h>
00017 #include "cvt_V1190.h"
00018 
00020 // File local defines
00022 
00024 // Output buffer macros
00026 #define V1190_DATA_TYPE_MSK                             0xf8000000              
00028 #define V1190_GLOBAL_HEADER                             0x40000000              
00029 #define V1190_GLOBAL_TRAILER                    0x80000000              
00030 #define V1190_TDC_HEADER                                0x08000000              
00031 #define V1190_TDC_MEASURE                               0x00000000              
00032 #define V1190_TDC_ERROR                                 0x20000000              
00033 #define V1190_TDC_TRAILER                               0x18000000              
00034 #define V1190_GLOBAL_TRIGGER_TIME               0x88000000              
00035 #define V1190_FILLER                                    0xc0000000              
00037 #define IS_GLOBAL_HEADER(data)                  ((data& V1190_DATA_TYPE_MSK)== V1190_GLOBAL_HEADER)                     
00038 #define IS_GLOBAL_TRAILER(data)                 ((data& V1190_DATA_TYPE_MSK)== V1190_GLOBAL_TRAILER)            
00039 #define IS_TDC_HEADER(data)                             ((data& V1190_DATA_TYPE_MSK)== V1190_TDC_HEADER)                        
00040 #define IS_TDC_MEASURE(data)                    ((data& V1190_DATA_TYPE_MSK)== V1190_TDC_MEASURE)                       
00041 #define IS_TDC_ERROR(data)                              ((data& V1190_DATA_TYPE_MSK)== V1190_TDC_ERROR)                         
00042 #define IS_TDC_TRAILER(data)                    ((data& V1190_DATA_TYPE_MSK)== V1190_TDC_TRAILER)                       
00043 #define IS_GLOBAL_TRIGGER_TIME(data)    ((data& V1190_DATA_TYPE_MSK)== V1190_GLOBAL_TRIGGER_TIME)       
00044 #define IS_FILLER(data)                                 ((data& V1190_DATA_TYPE_MSK)== V1190_FILLER)                            
00046 #define GET_EVENT_COUNT(data)                   ((UINT32)((((UINT32)data)>>5)& 0x003fffff))                                     
00048 
00049 // Static variables declaration
00050 
00051 
00053 
00058 
00059 static const cvt_reg_table CVT_V1190_REG_TABLE[]=
00060 {
00061         {CVT_V1190_OUT_BUFFER_ADD,                      CVT_V1190_OUT_BUFFER_AM,                CVT_V1190_OUT_BUFFER_DATA_SIZE},                                
00062         {CVT_V1190_CONTROL_ADD,                         CVT_V1190_CONTROL_AM,                   CVT_V1190_CONTROL_DATA_SIZE},                                   
00063         {CVT_V1190_STATUS_ADD,                          CVT_V1190_STATUS_AM,                    CVT_V1190_STATUS_DATA_SIZE},                                    
00064         {CVT_V1190_INT_LEVEL_ADD,                       CVT_V1190_INT_LEVEL_AM,                 CVT_V1190_INT_LEVEL_DATA_SIZE},                                 
00065         {CVT_V1190_INT_VECTOR_ADD,                      CVT_V1190_INT_VECTOR_AM,                CVT_V1190_INT_VECTOR_DATA_SIZE},                                
00066         {CVT_V1190_GEO_ADDRESS_ADD,                     CVT_V1190_GEO_ADDRESS_AM,               CVT_V1190_GEO_ADDRESS_DATA_SIZE},                               
00067         {CVT_V1190_MCST_CBLT_ADDRESS_ADD,       CVT_V1190_MCST_CBLT_ADDRESS_AM, CVT_V1190_MCST_CBLT_ADDRESS_DATA_SIZE},                 
00068         {CVT_V1190_MCST_CBLT_CTRL_ADD,          CVT_V1190_MCST_CBLT_CTRL_AM,    CVT_V1190_MCST_CBLT_CTRL_DATA_SIZE},                    
00069         {CVT_V1190_MOD_RESET_ADD,                       CVT_V1190_MOD_RESET_AM,                 CVT_V1190_MOD_RESET_DATA_SIZE},                                 
00070         {CVT_V1190_SW_CLEAR_ADD,                        CVT_V1190_SW_CLEAR_AM,                  CVT_V1190_SW_CLEAR_DATA_SIZE},                                  
00071         {CVT_V1190_SW_EVENT_RESET_ADD,          CVT_V1190_SW_EVENT_RESET_AM,    CVT_V1190_SW_EVENT_RESET_DATA_SIZE},                    
00072         {CVT_V1190_SW_TRIGGER_ADD,                      CVT_V1190_SW_TRIGGER_AM,                CVT_V1190_SW_TRIGGER_DATA_SIZE},                                
00073         {CVT_V1190_EVENT_COUNTER_ADD,           CVT_V1190_EVENT_COUNTER_AM,             CVT_V1190_EVENT_COUNTER_DATA_SIZE},                             
00074         {CVT_V1190_EVENT_STORED_ADD,            CVT_V1190_EVENT_STORED_AM,              CVT_V1190_EVENT_STORED_DATA_SIZE},                              
00075         {CVT_V1190_ALMOST_FULL_LVL_ADD,         CVT_V1190_ALMOST_FULL_LVL_AM,   CVT_V1190_ALMOST_FULL_LVL_DATA_SIZE},                   
00076         {CVT_V1190_BLT_EVENT_NUM_ADD,           CVT_V1190_BLT_EVENT_NUM_AM,             CVT_V1190_BLT_EVENT_NUM_DATA_SIZE},                             
00077         {CVT_V1190_FW_REV_ADD,                          CVT_V1190_FW_REV_AM,                    CVT_V1190_FW_REV_DATA_SIZE},                                    
00078         {CVT_V1190_TESTREG_ADD,                         CVT_V1190_TESTREG_AM,                   CVT_V1190_TESTREG_DATA_SIZE},                                   
00079         {CVT_V1190_OUT_PROG_CTRL_ADD,           CVT_V1190_OUT_PROG_CTRL_AM,             CVT_V1190_OUT_PROG_CTRL_DATA_SIZE},                             
00080         {CVT_V1190_MICRO_ADD,                           CVT_V1190_MICRO_AM,                             CVT_V1190_MICRO_DATA_SIZE},                                             
00081         {CVT_V1190_MICRO_HND_ADD,                       CVT_V1190_MICRO_HND_AM,                 CVT_V1190_MICRO_HND_DATA_SIZE},                                 
00082         {CVT_V1190_SEL_FLASH_ADD,                       CVT_V1190_SEL_FLASH_AM,                 CVT_V1190_SEL_FLASH_DATA_SIZE},                                 
00083         {CVT_V1190_FLASH_ADD,                           CVT_V1190_FLASH_AM,                             CVT_V1190_FLASH_DATA_SIZE},                                             
00084         {CVT_V1190_COMP_SRAM_PAGE_ADD,          CVT_V1190_COMP_SRAM_PAGE_AM,    CVT_V1190_COMP_SRAM_PAGE_DATA_SIZE},                    
00085         {CVT_V1190_EVENT_FIFO_ADD,                      CVT_V1190_EVENT_FIFO_AM,                CVT_V1190_EVENT_FIFO_DATA_SIZE},                                
00086         {CVT_V1190_EVENT_FIFO_STORED_ADD,       CVT_V1190_EVENT_FIFO_STORED_AM, CVT_V1190_EVENT_FIFO_STORED_DATA_SIZE},                 
00087         {CVT_V1190_EVENT_FIFO_STATUS_ADD,       CVT_V1190_EVENT_FIFO_STATUS_AM, CVT_V1190_EVENT_FIFO_STATUS_DATA_SIZE},                 
00088         {CVT_V1190_DUMMY32_ADD,                         CVT_V1190_DUMMY32_AM,                   CVT_V1190_DUMMY32_DATA_SIZE},                                   
00089         {CVT_V1190_DUMMY16_ADD,                         CVT_V1190_DUMMY16_AM,                   CVT_V1190_DUMMY16_DATA_SIZE},                                   
00090         {CVT_V1190_ROM_OUI_MSB_ADD,                     CVT_V1190_ROM_OUI_MSB_AM,               CVT_V1190_ROM_OUI_MSB_DATA_SIZE},                               
00091         {CVT_V1190_ROM_OUI_ADD,                         CVT_V1190_ROM_OUI_AM,                   CVT_V1190_ROM_OUI_DATA_SIZE},                                   
00092         {CVT_V1190_ROM_OUI_LSB_ADD,                     CVT_V1190_ROM_OUI_LSB_AM,               CVT_V1190_ROM_OUI_LSB_DATA_SIZE},                               
00093         {CVT_V1190_ROM_VERSION_ADD,                     CVT_V1190_ROM_VERSION_AM,               CVT_V1190_ROM_VERSION_DATA_SIZE},                               
00094         {CVT_V1190_ROM_BOARD_ID_MSB_ADD,        CVT_V1190_ROM_BOARD_ID_MSB_AM,  CVT_V1190_ROM_BOARD_ID_MSB_DATA_SIZE},                  
00095         {CVT_V1190_ROM_BOARD_ID_ADD,            CVT_V1190_ROM_BOARD_ID_AM,              CVT_V1190_ROM_BOARD_ID_DATA_SIZE},                              
00096         {CVT_V1190_ROM_BOARD_ID_LSB_ADD,        CVT_V1190_ROM_BOARD_ID_LSB_AM,  CVT_V1190_ROM_BOARD_ID_LSB_DATA_SIZE},                  
00097         {CVT_V1190_ROM_REVISION_3_ADD,          CVT_V1190_ROM_REVISION_3_AM,    CVT_V1190_ROM_REVISION_3_DATA_SIZE},                    
00098         {CVT_V1190_ROM_REVISION_2_ADD,          CVT_V1190_ROM_REVISION_2_AM,    CVT_V1190_ROM_REVISION_2_DATA_SIZE},                    
00099         {CVT_V1190_ROM_REVISION_1_ADD,          CVT_V1190_ROM_REVISION_1_AM,    CVT_V1190_ROM_REVISION_1_DATA_SIZE},                    
00100         {CVT_V1190_ROM_REVISION_0_ADD,          CVT_V1190_ROM_REVISION_0_AM,    CVT_V1190_ROM_REVISION_0_DATA_SIZE},                    
00101         {CVT_V1190_ROM_SERIAL_MSB_ADD,          CVT_V1190_ROM_SERIAL_MSB_AM,    CVT_V1190_ROM_SERIAL_MSB_DATA_SIZE},                    
00102         {CVT_V1190_ROM_SERIAL_LSB_ADD,          CVT_V1190_ROM_SERIAL_LSB_AM,    CVT_V1190_ROM_SERIAL_LSB_DATA_SIZE},                    
00103 };
00105 // Static methods declaration
00107 
00109 // Global visible variables declaration
00111 
00113 //
00114 //     B O A R D S   H A N D L I N G
00115 //
00117 
00119 // 
00121 BOOL cvt_V1190_open( cvt_V1190_data* p_data, UINT16 base_address, long vme_handle, CVT_V1190_TYPES type)
00122 {
00123         memset( p_data, 0, sizeof( cvt_V1190_data));
00124         // Check board type
00125         switch( type)
00126         {
00127         case CVT_V1190_TYPE_A:                                          
00128         case CVT_V1190_TYPE_B:                                          
00129                 break;
00130         default:
00131                 TRACE1( "cvt_V1190_open: bad board type: %d\n", type);
00132                 return FALSE;
00133         }
00134         // basic data initialization
00135         if( !cvt_board_open( &p_data->m_common_data, base_address, vme_handle, CVT_V1190_REG_TABLE))
00136                 return FALSE;
00137         // board specific data initialization
00138         p_data->m_common_data.set_MCST_CBLT= cvt_V1190_set_MCST_CBLT;
00139         p_data->m_type= type;
00140 
00141 #ifdef CVT_V1190_USE_DATA_QUEUE
00142         p_data->m_queue= malloc( CVT_V1190_QUEUE_SIZE_DWORD* sizeof( UINT32));  
00143         if( p_data->m_queue== NULL)
00144         {
00145                 TRACE( "cvt_V1190_open: cannot allocate queue buffer\n");
00146                 return FALSE;
00147         }
00148         memset( p_data->m_queue, 0, CVT_V1190_QUEUE_SIZE_DWORD* sizeof( UINT32));
00149 #endif
00150         
00151         return TRUE;
00152 }
00153 
00155 // 
00157 BOOL cvt_V1190_close( cvt_V1190_data* p_data)
00158 {
00159 #ifdef CVT_V1190_USE_DATA_QUEUE
00160         if( p_data->m_queue!= NULL)
00161         {
00162                 free( p_data->m_queue);
00163         }
00164 #endif
00165         if( !cvt_board_close( &p_data->m_common_data))
00166                 return FALSE;
00167         return TRUE;
00168 }
00170 //
00171 //     L E V E L   0   A P I s
00172 //
00174 
00176 //
00177 //     L E V E L   1   A P I s
00178 //
00180 
00182 // 
00184 BOOL vme_board_1190_write_2_micro( cvt_V1190_data* p_data, UINT16 ope_code, const UINT16* p_params, int num_params)
00185 {
00186         UINT16 micro_hnd= 0;
00187         // wait for micro register write ok
00188         do
00189         {
00190                 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_HND_INDEX, &micro_hnd))
00191                 {
00192                         return FALSE;
00193                 }
00194         } while( !(micro_hnd& CVT_V1190_MICRO_HND_WRITEOK_MSK));
00195         // write opcode to micro register
00196         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MICRO_INDEX, &ope_code))
00197         {
00198                 return FALSE;
00199         }
00200         // write ope cod
00201         while( num_params--)
00202         {
00203                 // wait for micro register write ok
00204                 do
00205                 {
00206                         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_HND_INDEX, &micro_hnd))
00207                         {
00208                                 return FALSE;
00209                         }
00210                 } while( !(micro_hnd& CVT_V1190_MICRO_HND_WRITEOK_MSK));
00211                 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MICRO_INDEX, p_params++))
00212                 {
00213                         return FALSE;
00214                 }
00215         }
00216         return TRUE;
00217 }
00218 
00220 // 
00222 static BOOL vme_board_1190_read_from_micro( cvt_V1190_data* p_data, UINT16 ope_code, UINT16* p_params, int num_params)
00223 {
00224         UINT16 micro_hnd= 0;
00225         // wait for micro register write ok
00226         do
00227         {
00228                 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_HND_INDEX, &micro_hnd))
00229                 {
00230                         return FALSE;
00231                 }
00232         } while( !(micro_hnd& CVT_V1190_MICRO_HND_WRITEOK_MSK));
00233         // write opcode to micro register
00234         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MICRO_INDEX, &ope_code))
00235         {
00236                 return FALSE;
00237         }
00238         // read ope code 
00239         while( num_params--)
00240         {
00241                 // wait for micro register read ok
00242                 do
00243                 {
00244                         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_HND_INDEX, &micro_hnd))
00245                         {
00246                                 return FALSE;
00247                         }
00248                 } while( !(micro_hnd& CVT_V1190_MICRO_HND_READOK_MSK));
00249                 if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_MICRO_INDEX, p_params++))
00250                 {
00251                         return FALSE;
00252                 }
00253         }
00254         return TRUE;
00255 }
00256 
00258 // 
00260 BOOL cvt_V1190_set_bitmask_control( cvt_V1190_data* p_data, CVT_V1190_CONTROL_MSK value)
00261 {
00262         UINT16 reg_value= value;
00263         // set bitmask to register
00264         if( !cvt_set_bitmask( &p_data->m_common_data, CVT_V1190_CONTROL_ADD, &reg_value, CVT_V1190_CONTROL_AM, CVT_V1190_CONTROL_DATA_SIZE))
00265         {
00266                 TRACE( "V1190 CVT_V1190_CONTROL_SET failed !\n");
00267                 return FALSE;
00268         }
00269         return TRUE;
00270 }
00271 
00273 // 
00275 BOOL cvt_V1190_clear_bitmask_control( cvt_V1190_data* p_data, CVT_V1190_CONTROL_MSK value)
00276 {
00277         UINT16 reg_value= value;
00278         // set bitmask to register
00279         if( !cvt_clear_bitmask( &p_data->m_common_data, CVT_V1190_CONTROL_ADD, &reg_value, CVT_V1190_CONTROL_AM, CVT_V1190_CONTROL_DATA_SIZE))
00280         {
00281                 TRACE( "V1190 CVT_V1190_CONTROL_CLEAR failed !\n");
00282                 return FALSE;
00283         }
00284         return TRUE;
00285 }
00286 
00288 //
00289 //     L E V E L   2   A P I s
00290 //
00292 
00294 // 
00296 BOOL cvt_V1190_set_windows_width( cvt_V1190_data* p_data, UINT16 value)
00297 {
00298         UINT16 reg_value= (UINT16)value;
00299         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_WIN_WIDTH_OPCODE, &reg_value, 1))
00300         {
00301                 TRACE( "V1190 WND_WIDTH write failed !\n");
00302                 return FALSE;
00303         }
00304         return TRUE;
00305 }
00306 
00308 // 
00310 BOOL cvt_V1190_set_windows_offset( cvt_V1190_data* p_data, UINT16 value)
00311 {
00312         UINT16 reg_value= (UINT16)value;
00313         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_WIN_OFFSET_OPCODE, &reg_value, 1))
00314         {
00315                 TRACE( "V1190 WND_OFFSET write failed !\n");
00316                 return FALSE;
00317         }
00318         return TRUE;
00319 }
00320 
00322 // 
00324 BOOL cvt_V1190_get_enable_pattern( cvt_V1190_data* p_data, UINT16 *p_enable_msk)
00325 {
00326         int num_tdc= 0;
00327 
00328         switch( p_data->m_type)
00329         {
00330         case CVT_V1190_TYPE_A:                                          
00331                 num_tdc= CVT_V1190_NUM_TDC_A;
00332                 break;
00333         case CVT_V1190_TYPE_B:                                          
00334                 num_tdc= CVT_V1190_NUM_TDC_B;
00335                 break;
00336         default:
00337                 TRACE1( "cvt_V1190_set_enable_pattern: bad board type: %d\n", p_data->m_type);
00338                 return FALSE;
00339         }
00340         //
00341         // read channel enable pattern
00342         if( !vme_board_1190_read_from_micro( p_data, CVT_V1190_WRITE_EN_PATTERN_OPCODE, p_enable_msk, num_tdc* 4))
00343         {
00344                 TRACE( "V1190 EN_CHANNEL_MSK write failed !\n");
00345                 return FALSE;
00346         }
00347 
00348         return TRUE;
00349 }
00350 
00352 // 
00354 BOOL cvt_V1190_set_trigger_match( cvt_V1190_data* p_data)
00355 {
00356         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_TRG_MATCH_OPCODE, NULL, 0))
00357         {
00358                 TRACE( "V1190 TRG_MATCH write failed !\n");
00359                 return FALSE;
00360         }
00361         return TRUE;
00362 }
00363 
00365 // 
00367 BOOL cvt_V1190_set_head_trail_enable( cvt_V1190_data* p_data)
00368 {
00369         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_EN_HEAD_TRAILER_OPCODE, 0, 0))
00370         {
00371                 TRACE( "V1190 TDC_HEAD_TRAIL_ENABLE write failed !\n");
00372                 return FALSE;
00373         }
00374         return TRUE;
00375 }
00376 
00378 // 
00380 BOOL cvt_V1190_set_head_trail_disable( cvt_V1190_data* p_data)
00381 {
00382         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_DIS_HEAD_TRAILER_OPCODE, 0, 0))
00383         {
00384                 TRACE( "V1190 TDC_HEAD_TRAIL_DISABLE write failed !\n");
00385                 return FALSE;
00386         }
00387         return TRUE;
00388 }
00389 
00391 // 
00393 BOOL cvt_V1190_read_MEB( cvt_V1190_data* p_data, void* p_buff, UINT32* p_buff_size)
00394 {
00395         if( !cvt_FIFO_BLT_read( &p_data->m_common_data, CVT_V1190_OUT_BUFFER_ADD, p_buff, *p_buff_size, p_buff_size, CVT_V1190_OUT_BUFFER_AM, CVT_V1190_OUT_BUFFER_DATA_SIZE))
00396         {
00397                 return FALSE;
00398         }
00399         // V1190 return a filler if output buffer empty, so discard it
00400         if( *p_buff_size== sizeof( UINT32))
00401         {
00402                 if( IS_FILLER( *((UINT32*)p_buff)))
00403                         *p_buff_size= 0;
00404         }
00405         return TRUE;
00406 }
00407 
00409 // 
00411 BOOL cvt_V1190_set_continuous_acquisition_mode( cvt_V1190_data* p_data, CVT_V1190_EDGE_DETECTION_ENUM edge_detection, CVT_V1190_PAIR_RES_WIDTH_ENUM res_width, const UINT16 *p_enable_msk)
00412 {
00413         UINT16 reg_value;
00414         //
00415         // write continuous storage mode opcode
00416         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_CONT_STORE_OPCODE, NULL, 0))
00417         {
00418                 TRACE( "V1190 CVT_V1190_CONT_STORE_OPCODE write failed !\n");
00419                 return FALSE;
00420         }
00421 
00422         //
00423         // Edge detection
00424         switch( edge_detection)
00425         {
00426         case CVT_V1190_ED_PAIR_MODE:                    
00427         case CVT_V1190_ED_TRAILING_ONLY:                
00428         case CVT_V1190_ED_LEADING_ONLY:                 
00429         case CVT_V1190_ED_TRAILING_AND_LEADING: 
00430                 break;
00431         default:
00432                 TRACE1( "V1190 cvt_V1190_set_continuous_acquisition_mode bad edge detection type '%d' !\n", edge_detection);
00433                 return FALSE;
00434         }
00435         reg_value= edge_detection;      
00436         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_DETECTION_OPCODE, &reg_value, 1))
00437         {
00438                 TRACE( "V1190 CVT_V1190_SET_DETECTION_OPCODE write failed !\n");
00439                 return FALSE;
00440         }
00441 
00442         // 
00443         // Resolution width
00444         switch( res_width)
00445         {
00446         case CVT_V1190_PRW_100PS:                       
00447         case CVT_V1190_PRW_200PS:                       
00448         case CVT_V1190_PRW_400PS:                       
00449         case CVT_V1190_PRW_800PS:                       
00450         case CVT_V1190_PRW_1_6NS:                       
00451         case CVT_V1190_PRW_3_12NS:                      
00452         case CVT_V1190_PRW_6_25NS:                      
00453         case CVT_V1190_PRW_12_5NS:                      
00454         case CVT_V1190_PRW_25NS:                        
00455         case CVT_V1190_PRW_50NS:                        
00456         case CVT_V1190_PRW_100NS:                       
00457         case CVT_V1190_PRW_200NS:                       
00458         case CVT_V1190_PRW_400NS:                       
00459         case CVT_V1190_PRW_800NS:                       
00460                 break;
00461         default:
00462                 TRACE1( "V1190 cvt_V1190_set_continuous_acquisition_mode bad resolution width '%d' !\n", res_width);
00463                 return FALSE;
00464         }
00465         reg_value= 0;
00466         CVT_V1190_SET_PAIR_RES_WITH( reg_value, res_width);
00467         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_PAIR_RES_OPCODE, &reg_value, 1))
00468         {
00469                 TRACE( "V1190 CVT_V1190_SET_PAIR_RES_OPCODE write failed !\n");
00470                 return FALSE;
00471         }
00472 
00473         //
00474         // Channel enable mask
00475         if( p_enable_msk)
00476         {
00477                 if( !cvt_V1190_set_channel_enable( p_data, p_enable_msk))
00478                 {
00479                         return FALSE;
00480                 }
00481         }
00482 
00483         return TRUE;
00484 }
00485 
00487 // 
00489 BOOL cvt_V1190_set_trigger_matching_acquisition_mode( cvt_V1190_data* p_data, UINT16 window_width, UINT16 window_offset, UINT16 extra_search_margin, UINT16 reject_margin, CVT_V1190_EDGE_DETECTION_ENUM edge_detection, CVT_V1190_PAIR_RES_WIDTH_ENUM res_width, const UINT16 *p_enable_msk, BOOL header_trailer_enable, BOOL empty_event_enable, BOOL trigger_time_tag_enable)
00490 {
00491         UINT16 reg_value;
00492         UINT16 set_msk= 0;
00493         UINT16 clear_msk= 0;
00494         //
00495         // set trigger matching mode
00496         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_TRG_MATCH_OPCODE, NULL, 0))
00497         {
00498                 TRACE( "V1190 CVT_V1190_TRG_MATCH_OPCODE write failed !\n");
00499                 return FALSE;
00500         }
00501         //
00502         // Set window width
00503         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_WIN_WIDTH_OPCODE, &window_width, 1))
00504         {
00505                 TRACE( "V1190 CVT_V1190_SET_WIN_WIDTH_OPCODE write failed !\n");
00506                 return FALSE;
00507         }
00508         //
00509         // Set window offset
00510         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_WIN_OFFSET_OPCODE, &window_offset, 1))
00511         {
00512                 TRACE( "V1190 CVT_V1190_SET_WIN_OFFSET_OPCODE write failed !\n");
00513                 return FALSE;
00514         }
00515         //
00516         // Set extra search margin micro opcode
00517         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_SW_MARGIN_OPCODE, &extra_search_margin, 1))
00518         {
00519                 TRACE( "V1190 CVT_V1190_SET_SW_MARGIN_OPCODE write failed !\n");
00520                 return FALSE;
00521         }
00522         //
00523         // Set reject margin micro opcode 
00524         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_REJ_MARGIN_OPCODE, &reject_margin, 1))
00525         {
00526                 TRACE( "V1190 CVT_V1190_SET_REJ_MARGIN_OPCODE write failed !\n");
00527                 return FALSE;
00528         }
00529         //
00530         // Edge detection
00531         switch( edge_detection)
00532         {
00533         case CVT_V1190_ED_PAIR_MODE:                    
00534         case CVT_V1190_ED_TRAILING_ONLY:                
00535         case CVT_V1190_ED_LEADING_ONLY:                 
00536         case CVT_V1190_ED_TRAILING_AND_LEADING: 
00537                 break;
00538         default:
00539                 TRACE1( "V1190 cvt_V1190_set_continuous_acquisition_mode bad edge detection type '%d' !\n", edge_detection);
00540                 return FALSE;
00541         }
00542         reg_value= edge_detection;      
00543         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_DETECTION_OPCODE, &reg_value, 1))
00544         {
00545                 TRACE( "V1190 CVT_V1190_SET_DETECTION_OPCODE write failed !\n");
00546                 return FALSE;
00547         }
00548         // 
00549         // Resolution width
00550         switch( res_width)
00551         {
00552         case CVT_V1190_PRW_100PS:                       
00553         case CVT_V1190_PRW_200PS:                       
00554         case CVT_V1190_PRW_400PS:                       
00555         case CVT_V1190_PRW_800PS:                       
00556         case CVT_V1190_PRW_1_6NS:                       
00557         case CVT_V1190_PRW_3_12NS:                      
00558         case CVT_V1190_PRW_6_25NS:                      
00559         case CVT_V1190_PRW_12_5NS:                      
00560         case CVT_V1190_PRW_25NS:                        
00561         case CVT_V1190_PRW_50NS:                        
00562         case CVT_V1190_PRW_100NS:                       
00563         case CVT_V1190_PRW_200NS:                       
00564         case CVT_V1190_PRW_400NS:                       
00565         case CVT_V1190_PRW_800NS:                       
00566                 break;
00567         default:
00568                 TRACE1( "V1190 cvt_V1190_set_continuous_acquisition_mode bad resolution width '%d' !\n", res_width);
00569                 return FALSE;
00570         }
00571         reg_value= 0;
00572         CVT_V1190_SET_PAIR_RES_WITH( reg_value, res_width);
00573         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_SET_PAIR_RES_OPCODE, &reg_value, 1))
00574         {
00575                 TRACE( "V1190 CVT_V1190_SET_PAIR_RES_OPCODE write failed !\n");
00576                 return FALSE;
00577         }
00578         //
00579         // Channel enable pattern
00580         //
00581         // Channel enable mask
00582         if( p_enable_msk)
00583         {
00584                 if( !cvt_V1190_set_channel_enable( p_data, p_enable_msk))
00585                 {
00586                         return FALSE;
00587                 }
00588         }
00589         //
00590         // enable/disable header trailer
00591         if( header_trailer_enable)
00592         {
00593                 if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_EN_HEAD_TRAILER_OPCODE, NULL, 0))
00594                 {
00595                         TRACE( "V1190 CVT_V1190_EN_HEAD_TRAILER_OPCODE write failed !\n");
00596                         return FALSE;
00597                 }
00598         }
00599         else
00600         {
00601                 if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_DIS_HEAD_TRAILER_OPCODE, NULL, 0))
00602                 {
00603                         TRACE( "V1190 CVT_V1190_DIS_HEAD_TRAILER_OPCODE write failed !\n");
00604                         return FALSE;
00605                 }
00606         }
00607 
00608         //
00609         // Empty event enable
00610         set_msk|= ( empty_event_enable)? CVT_V1190_CTRL_EMPTY_EVENT_MSK: 0;
00611         clear_msk|= ( empty_event_enable)? 0: CVT_V1190_CTRL_EMPTY_EVENT_MSK;
00612         //
00613         // Trigger time tag enable
00614         set_msk|= ( trigger_time_tag_enable)? CVT_V1190_CTRL_TRIGGER_TIME_TAG_ENABLE_MSK: 0;
00615         clear_msk|= ( trigger_time_tag_enable)? 0: CVT_V1190_CTRL_TRIGGER_TIME_TAG_ENABLE_MSK;
00616 
00617         if( set_msk)
00618         {
00619                 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1190_CONTROL_INDEX, &set_msk))
00620                 {
00621                         TRACE( "V1190 CVT_V1190_CONTROL bitmask set failed !\n");
00622                         return FALSE;
00623                 }
00624         }
00625         if( clear_msk)
00626         {
00627                 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1190_CONTROL_INDEX, &clear_msk))
00628                 {
00629                         TRACE( "V1190 CVT_V1190_CONTROL bitmask clear failed !\n");
00630                         return FALSE;
00631                 }
00632         }
00633 
00634         return TRUE;
00635 }
00636 
00638 //
00640 BOOL cvt_V1190_set_interrupt( cvt_V1190_data* p_data, UINT8 level, UINT8 vector)
00641 {
00642         UINT16 reg_value;
00643         //
00644         // interrupt level
00645         reg_value= level& 0x07;
00646         if( level!= reg_value)
00647         {
00648                 TRACE( "V1190 bad interrupt level !\n");
00649                 return FALSE;
00650         }
00651         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_INT_LEVEL_INDEX, &reg_value))
00652         {
00653                 TRACE( "V1190 CVT_V1190_INT_LEVEL write failed !\n");
00654                 return FALSE;
00655         }
00656         //
00657         // interrupt vector
00658         reg_value= vector;
00659         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_INT_VECTOR_INDEX, &reg_value))
00660         {
00661                 TRACE( "V1190 CVT_V1190_INT_VECTOR write failed !\n");
00662                 return FALSE;
00663         }
00664 
00665         return TRUE;
00666 }
00667 
00669 //
00671 BOOL cvt_V1190_set_readout_mode( cvt_V1190_data* p_data, BOOL bus_error_enable, BOOL align64_enable, UINT8 blt_event_number)
00672 {
00673         UINT16 reg_value;
00674         UINT16 set_msk= 0;
00675         UINT16 clear_msk= 0;
00676         
00677         //
00678         // Bus error
00679         set_msk|= ( bus_error_enable)? CVT_V1190_CTRL_BERR_ENABLE_MSK: 0;
00680         clear_msk|= ( bus_error_enable)? 0: CVT_V1190_CTRL_BERR_ENABLE_MSK;
00681         //
00682         // Align 64
00683         set_msk|= ( align64_enable)? CVT_V1190_CTRL_ALIGN64_MSK: 0;
00684         clear_msk|= ( align64_enable)? 0: CVT_V1190_CTRL_ALIGN64_MSK;
00685         
00686         //
00687         // bitmask set
00688         if( set_msk)
00689         {
00690                 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1190_CONTROL_INDEX, &set_msk))
00691                 {
00692                         TRACE( "V1190 CVT_V1190_CONTROL write failed !\n");
00693                         return FALSE;
00694                 }
00695         }
00696         //
00697         // bitmask clear
00698         if( clear_msk)
00699         {
00700                 // clear the enable bit
00701                 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1190_CONTROL_INDEX, &clear_msk))
00702                 {
00703                         TRACE( "V1190 CVT_V1190_CONTROL write failed !\n");
00704                         return FALSE;
00705                 }
00706         }
00707 
00708         //
00709         // BLT event number
00710         reg_value= blt_event_number;
00711         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_BLT_EVENT_NUM_INDEX, &reg_value))
00712         {
00713                 TRACE( "V1190 CVT_V1190_BLT_EVENT_NUM write failed !\n");
00714                 return FALSE;
00715         }
00716 
00717         return TRUE;
00718 }
00719 
00721 //
00723 BOOL cvt_V1190_get_status( cvt_V1190_data* p_data, BOOL *p_is_data_ready, BOOL *p_is_term_on, BOOL *p_is_buffer_full, BOOL *p_is_buffer_almost_full, CVT_V1190_STATUS_RES* p_resolution, UINT8* p_error_bitmask)
00724 {
00725         UINT16 reg_value= 0;
00726         //
00727         // read status register
00728         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_STATUS_INDEX, &reg_value))
00729         {
00730                 TRACE( "V1190 CVT_V1190_STATUS read failed !\n");
00731                 return FALSE;
00732         }
00733         *p_is_data_ready= ( reg_value& CVT_V1190_STS_DREADY_MSK)? TRUE: FALSE;
00734         *p_is_term_on= ( reg_value& CVT_V1190_STS_TERM_ON_MSK)? TRUE: FALSE;
00735         *p_is_buffer_full= ( reg_value& CVT_V1190_STS_FULL_MSK)? TRUE: FALSE;
00736         *p_is_buffer_almost_full= ( reg_value& CVT_V1190_STS_ALMOST_FULL_MSK)? TRUE: FALSE;
00737 
00738         *p_resolution= CVT_V1190_GET_STATUS_RES( reg_value);
00739         *p_error_bitmask= CVT_V1190_GET_STATUS_ERROR( reg_value);
00740 
00741         return TRUE;
00742 }
00743 
00745 //
00747 BOOL cvt_V1190_get_event_counter( cvt_V1190_data* p_data, UINT32* p_counter)
00748 {
00749         UINT32 reg_value;
00750         *p_counter= 0;
00751         // Event Counter
00752         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_EVENT_COUNTER_INDEX, &reg_value))
00753         {
00754                 TRACE( "V1190 CVT_V1190_EVENT_COUNTER read failed !\n");
00755                 return FALSE;
00756         }
00757         *p_counter= reg_value;
00758 
00759         return TRUE;
00760 }
00761 
00763 //
00765 BOOL cvt_V1190_get_event_stored( cvt_V1190_data* p_data, UINT16* p_counter)
00766 {
00767         UINT16 reg_value;
00768         *p_counter= 0;
00769         // Event stored
00770         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_EVENT_STORED_INDEX, &reg_value))
00771         {
00772                 TRACE( "V1190 CVT_V1190_EVENT_STORED read failed !\n");
00773                 return FALSE;
00774         }
00775         *p_counter= reg_value;
00776 
00777         return TRUE;
00778 }
00779 
00780 
00782 //
00784 BOOL cvt_V1190_get_system_info( cvt_V1190_data* p_data, UINT16 *p_firmware_rev, UINT16 *p_tdc_id_buff, UINT16 *p_micro_firmware_rev, UINT16 *p_serial_number)
00785 {
00786         UINT16 reg_value= 0;
00787         int num_tdc= 0;
00788 
00789         switch( p_data->m_type)
00790         {
00791         case CVT_V1190_TYPE_A:                                          
00792                 num_tdc= CVT_V1190_NUM_TDC_A;
00793                 break;
00794         case CVT_V1190_TYPE_B:                                          
00795                 num_tdc= CVT_V1190_NUM_TDC_B;
00796                 break;
00797         default:
00798                 TRACE1( "cvt_V1190_get_system_info: bad board type: %d\n", p_data->m_type);
00799                 return FALSE;
00800         }
00801         //
00802         // Firmware revision register
00803         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_FW_REV_INDEX, &reg_value))
00804         {
00805                 TRACE( "V1190 CVT_V1190_FW_REV read failed !\n");
00806                 return FALSE;
00807         }
00808         *p_firmware_rev= (( reg_value& 0x00f0)<< 4)|( reg_value& 0x000f);
00809         //
00810         // TDC IDs
00811         while( num_tdc--)
00812         {
00813                 if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_READ_TDC_ID_OPCODE+ num_tdc, &reg_value, 1))
00814                 {
00815                         TRACE( "V1190 CVT_V1190_READ_TDC_ID_OPCODE opcode read failed !\n");
00816                         return FALSE;
00817                 }
00818                 p_tdc_id_buff[ num_tdc]= (( reg_value& 0x00f0)<< 4)|( reg_value& 0x000f);
00819         }
00820         //
00821         // Microcontroller firmware revision
00822         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_MICROCONTROLLER_FW_OPCODE, &reg_value, 1))
00823         {
00824                 TRACE( "V1190 CVT_V1190_MICROCONTROLLER_FW_OPCODE opcode read failed !\n");
00825                 return FALSE;
00826         }
00827         *p_micro_firmware_rev= (( reg_value& 0x00f0)<< 4)|( reg_value& 0x000f);
00828         //
00829         // Serial number
00830         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_ROM_SERIAL_LSB_INDEX, &reg_value))
00831         {
00832                 TRACE( "V1190 CVT_V1190_ROM_SERIAL_LSB read failed !\n");
00833                 return FALSE;
00834         }
00835         *p_serial_number= reg_value& 0x00ff;
00836         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1190_ROM_SERIAL_MSB_INDEX, &reg_value))
00837         {
00838                 TRACE( "V1190 CVT_V1190_ROM_SERIAL_MSB read failed !\n");
00839                 return FALSE;
00840         }
00841         *p_serial_number|= (reg_value& 0x00ff)<< 8;
00842         return TRUE;
00843 }
00844 
00846 // 
00848 BOOL cvt_V1190_data_clear( cvt_V1190_data* p_data)
00849 {
00850         UINT16 reg_value= 0;
00851         // force software clear
00852         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_SW_CLEAR_INDEX, &reg_value))
00853         {
00854                 TRACE( "V1190 SW_CLEAR write failed !\n");
00855                 return FALSE;
00856         }
00857         return TRUE;
00858 }
00859 
00861 // 
00863 BOOL cvt_V1190_module_reset( cvt_V1190_data* p_data)
00864 {
00865         UINT16 reg_value= 0;
00866         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MOD_RESET_INDEX, &reg_value))
00867         {
00868                 TRACE( "V1190 MOD_RESET write failed !\n");
00869                 return FALSE;
00870         }
00871         return TRUE;
00872 }
00873 
00875 // 
00877 BOOL cvt_V1190_set_channel_enable( cvt_V1190_data* p_data, const UINT16* p_enable_msk)
00878 {
00879         int num_tdc= 0;
00880 
00881         switch( p_data->m_type)
00882         {
00883         case CVT_V1190_TYPE_A:                                          
00884                 num_tdc= CVT_V1190_NUM_TDC_A;
00885                 break;
00886         case CVT_V1190_TYPE_B:                                          
00887                 num_tdc= CVT_V1190_NUM_TDC_B;
00888                 break;
00889         default:
00890                 TRACE1( "cvt_V1190_set_enable_pattern: bad board type: %d\n", p_data->m_type);
00891                 return FALSE;
00892         }
00893         //
00894         // write channel enable pattern
00895         if( !vme_board_1190_write_2_micro( p_data, CVT_V1190_WRITE_EN_PATTERN_OPCODE, p_enable_msk, num_tdc* 4))
00896         {
00897                 TRACE( "V1190 EN_CHANNEL_MSK write failed !\n");
00898                 return FALSE;
00899         }
00900         return TRUE;
00901 }
00902 
00904 // 
00906 BOOL cvt_V1190_set_almost_full( cvt_V1190_data* p_data, UINT16 almost_full_value)
00907 {
00908         UINT16 reg_value= 0;
00909         //
00910         // write the almost full register
00911         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_ALMOST_FULL_LVL_INDEX, &reg_value))
00912         {
00913                 TRACE( "V1190 CVT_V1190_ALMOST_FULL_LVL write failed !\n");
00914                 return FALSE;
00915         }
00916         return TRUE;
00917 }
00918 
00919 
00920 
00922 // 
00924 BOOL cvt_V1190_peek_event( cvt_V1190_data *p_data, UINT32 *out_buff, long *p_out_buff_size, UINT32 *p_event_count)
00925 {
00926         long in_org_pos= p_data->m_queue_ini;
00927         long out_org_pos= 0;
00928         int step= 0;
00929         UINT32 data;
00930         UINT32 found_count;
00931         long queue_ptr= in_org_pos;
00932         long out_buff_size= *p_out_buff_size;
00933         long num_word_to_read= 0;
00934         long delta_count;
00935 
00936         // scan input stream
00937         while( queue_ptr!= p_data->m_queue_end)
00938         {
00939                 data= p_data->m_queue[ queue_ptr];
00940                 if( ++queue_ptr>= CVT_V1190_QUEUE_SIZE_DWORD)
00941                 {
00942                         queue_ptr= 0;
00943                 }
00944                 switch( step)
00945                 {
00946                         case 0:
00947                                 //
00948                                 // wait for header
00949                                 if( !IS_GLOBAL_HEADER( data))
00950                                 {
00951                                         // misplaced data ?!?!?
00952                                         // skip it
00953                                         cvt_V1190_dequeue( p_data, NULL, 1);
00954                                         in_org_pos= queue_ptr;
00955                                         break;
00956                                 }
00957                                 // Global Header found:
00958                                 // EOB found
00959                                 // check event count
00960                                 found_count= GET_EVENT_COUNT( data)& CVT_BOARD_EVENT_COUNT_MSK;
00961                                 delta_count= ( found_count- *p_event_count+ (CVT_BOARD_EVENT_COUNT_MSK+ 1))% (CVT_BOARD_EVENT_COUNT_MSK+ 1);
00962 
00963                                 num_word_to_read= 1;
00964                                 ++step;
00965                                 break;
00966                         case 1:
00967                                 //
00968                                 // wait for EOB
00969                                 ++num_word_to_read;
00970                                 // check if EOB
00971                                 if( !IS_GLOBAL_TRAILER( data))
00972                                 {
00973                                         // channels data
00974                                         break;
00975                                 }
00976                                 //if( found_count> *p_event_count)
00977                                 if( delta_count> 0)
00978                                 {
00979                                         // reposition stream to start
00980                                         // p_data->m_queue_ini= in_org_pos;
00981                                         *p_out_buff_size= 0;
00982                                         *p_event_count= found_count;
00983                                         return TRUE;
00984                                 }
00985                                 //if( found_count== *p_event_count)
00986                                 if( !delta_count)
00987                                 {
00988                                         if( out_buff_size< num_word_to_read)
00989                                         {
00990                                                 // p_data->m_queue_ini= in_org_pos;
00991                                                 *p_out_buff_size= 0;
00992                                                 return FALSE;
00993                                         }
00994                                         // event count matching
00995                                         if( queue_ptr>= in_org_pos)
00996                                         {
00997                                                 memcpy( out_buff, p_data->m_queue+ in_org_pos, num_word_to_read*sizeof( UINT32));
00998                                                 // p_data->m_queue_ini= queue_ptr;
00999                                         }
01000                                         else
01001                                         {
01002                                                 // HACK rivedere < e <= 
01003                                                 long first_block_word= CVT_V1190_QUEUE_SIZE_DWORD- in_org_pos;
01004                                                 long second_block_word= num_word_to_read- first_block_word;
01005                                                 memcpy( out_buff, p_data->m_queue+ in_org_pos, first_block_word* sizeof(UINT32));
01006                                                 memcpy( out_buff+ first_block_word, p_data->m_queue, second_block_word* sizeof(UINT32));
01007                                                 // p_data->m_queue_ini= second_block_word;
01008                                         }
01009                                         *p_out_buff_size= num_word_to_read;
01010                                         // done
01011                                         return TRUE;
01012                                 }
01013                                 else
01014                                 {
01015                                         // event count is less then requested
01016                                         // skip it
01017                                         cvt_V1190_dequeue( p_data, NULL, num_word_to_read);
01018                                         // search for header again
01019                                         step= 0;
01020                                         TRACE1( "cvt_V1190_peek_event: skipped event %d\n", found_count);
01021                                 }
01022                                 break;
01023                 }
01024         }
01025         // p_data->m_queue_ini= in_org_pos;
01026         *p_out_buff_size= 0;
01027         return FALSE;
01028 }
01029 
01031 // 
01033 BOOL cvt_V1190_inqueue( cvt_V1190_data* p_data, const UINT32* in_buff, UINT32 in_buff_size)
01034 {
01035         if( !in_buff_size)
01036                 return TRUE;
01037         if( cvt_V1190_get_queue_free( p_data)< (long)in_buff_size)
01038         {
01039                 // No enough free space
01040                 return FALSE;
01041         }
01042         if( p_data->m_queue_end+ in_buff_size< CVT_V1190_QUEUE_SIZE_DWORD)
01043         {
01044                 memcpy( p_data->m_queue+ p_data->m_queue_end, in_buff, in_buff_size*sizeof( UINT32));
01045                 p_data->m_queue_end+= in_buff_size;
01046         }
01047         else
01048         {
01049                 long first_block_word= CVT_V1190_QUEUE_SIZE_DWORD- p_data->m_queue_end;
01050                 long second_block_word= in_buff_size- first_block_word;
01051                 memcpy( p_data->m_queue+ p_data->m_queue_end, in_buff, first_block_word* sizeof(UINT32));
01052                 memcpy( p_data->m_queue, in_buff+ first_block_word, second_block_word* sizeof(UINT32));
01053                 p_data->m_queue_end= second_block_word;
01054         }
01055         return TRUE;
01056 }
01057 
01059 // 
01061 BOOL cvt_V1190_dequeue( cvt_V1190_data* p_data, UINT32 *out_buff, UINT32 out_buff_size)
01062 {
01063         if( !out_buff_size)
01064                 return TRUE;
01065         if( cvt_V1190_get_queue_length( p_data)< (long)out_buff_size)
01066         {
01067                 // No enough data
01068                 return FALSE;
01069         }
01070         if( p_data->m_queue_ini+ out_buff_size< CVT_V1190_QUEUE_SIZE_DWORD)
01071         {
01072                 if( out_buff)
01073                 {
01074                         memcpy( out_buff, p_data->m_queue+ p_data->m_queue_ini, out_buff_size*sizeof( UINT32));
01075                 }
01076                 p_data->m_queue_ini+= out_buff_size;
01077         }
01078         else
01079         {
01080                 long first_block_word= CVT_V1190_QUEUE_SIZE_DWORD- p_data->m_queue_ini;
01081                 long second_block_word= out_buff_size- first_block_word;
01082                 if( out_buff)
01083                 {
01084                         memcpy( out_buff, p_data->m_queue+ p_data->m_queue_ini, first_block_word* sizeof(UINT32));
01085                         memcpy( out_buff+ first_block_word, p_data->m_queue, second_block_word* sizeof(UINT32));
01086                 }
01087                 p_data->m_queue_ini= second_block_word;
01088         }
01089         return TRUE;
01090 }
01091 
01093 // 
01095 long cvt_V1190_get_queue_free( cvt_V1190_data* p_data)
01096 {
01097         return (long)CVT_V1190_QUEUE_SIZE_DWORD- (( p_data->m_queue_end- p_data->m_queue_ini+ CVT_V1190_QUEUE_SIZE_DWORD)%CVT_V1190_QUEUE_SIZE_DWORD);
01098 }
01099 
01101 // 
01103 long cvt_V1190_get_queue_length( cvt_V1190_data* p_data)
01104 {
01105         return (long)(( p_data->m_queue_end- p_data->m_queue_ini+ CVT_V1190_QUEUE_SIZE_DWORD)%CVT_V1190_QUEUE_SIZE_DWORD);
01106 }
01107 
01109 //
01111 BOOL cvt_V1190_set_MCST_CBLT( cvt_V1190_data* p_data, UINT8 address, MCST_CBLT_board_pos pos)
01112 {
01113         UINT16 reg_value;
01114         //
01115         // MCST/CBLT address
01116         reg_value= address;
01117         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MCST_CBLT_ADDRESS_INDEX, &reg_value))
01118         {
01119                 TRACE( "V1190 CVT_V1190_MCST_CBLT_ADDRESS write failed !\n");
01120                 return FALSE;
01121         }
01122         //
01123         // MCST/CBLT control
01124         switch( pos)
01125         {
01126         case MCST_CBLT_board_pos_first:
01127                 reg_value= CVT_V1190_MCCTRL_FIRST_BOARD_MSK;
01128                 break;
01129         case MCST_CBLT_board_pos_mid:
01130                 reg_value= CVT_V1190_MCCTRL_MID_BOARD_MSK;
01131                 break;
01132         case MCST_CBLT_board_pos_last:
01133                 reg_value= CVT_V1190_MCCTRL_LAST_BOARD_MSK;
01134                 break;
01135         default:
01136                 TRACE1( "V1190 cvt_V1190_set_MCST_CBLT bad position indentifier '%d'!\n", pos);
01137                 return FALSE;
01138         }
01139         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1190_MCST_CBLT_CTRL_INDEX, &reg_value))
01140         {
01141                 TRACE( "V1190 CVT_V1190_MCST_CBLT_CTRL write failed !\n");
01142                 return FALSE;
01143         }
01144 
01145         return TRUE;
01146 }

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