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00015 #include <memory.h>
00016 #include <string.h>
00017 #include "cvt_V1495.h"
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00033
00034 static const cvt_reg_table CVT_V1495_REG_TABLE[]=
00035 {
00036 { CVT_V1495_CONTROL_ADD, CVT_V1495_CONTROL_AM, CVT_V1495_CONTROL_DATA_SIZE},
00037 { CVT_V1495_PORTA_EN_LOW_ADD, CVT_V1495_PORTA_EN_LOW_AM, CVT_V1495_PORTA_EN_LOW_DATA_SIZE},
00038 { CVT_V1495_PORTA_EN_HIGH_ADD, CVT_V1495_PORTA_EN_HIGH_AM, CVT_V1495_PORTA_EN_HIGH_DATA_SIZE},
00039 { CVT_V1495_PORTB_EN_LOW_ADD, CVT_V1495_PORTB_EN_LOW_AM, CVT_V1495_PORTB_EN_LOW_DATA_SIZE},
00040 { CVT_V1495_PORTB_EN_HIGH_ADD, CVT_V1495_PORTB_EN_HIGH_AM, CVT_V1495_PORTB_EN_HIGH_DATA_SIZE},
00041 { CVT_V1495_PORTD_EN_LOW_ADD, CVT_V1495_PORTD_EN_LOW_AM, CVT_V1495_PORTD_EN_LOW_DATA_SIZE},
00042 { CVT_V1495_PORTD_EN_HIGH_ADD, CVT_V1495_PORTD_EN_HIGH_AM, CVT_V1495_PORTD_EN_HIGH_DATA_SIZE},
00044 };
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00062 BOOL cvt_V1495_open( cvt_V1495_data* p_data, UINT16 base_address, long vme_handle)
00063 {
00064 memset( p_data, 0, sizeof( cvt_V1495_data));
00065
00066 if( !cvt_board_open( &p_data->m_common_data, base_address, vme_handle, CVT_V1495_REG_TABLE))
00067 return FALSE;
00068
00069
00070 return TRUE;
00071 }
00072
00074
00076 BOOL cvt_V1495_close( cvt_V1495_data* p_data)
00077 {
00078 if( !cvt_board_close( &p_data->m_common_data))
00079 return FALSE;
00080 return TRUE;
00081 }
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00098 BOOL cvt_V1495_set_control( cvt_V1495_data* p_data, UINT16 value)
00099 {
00100 UINT16 reg_value= value;
00101
00102 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_CONTROL_INDEX, ®_value))
00103 {
00104 TRACE( "V1495 CONTROL write failed !\n");
00105 return FALSE;
00106 }
00107 return TRUE;
00108 }
00109
00111
00113 BOOL cvt_V1495_set_port_A_enable( cvt_V1495_data* p_data, UINT32 value)
00114 {
00115 UINT16 reg_value_l= (UINT16)( value& 0xffff);
00116 UINT16 reg_value_h= (UINT16)( ((UINT32)value>>16)& 0xffff);
00117
00118
00119 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_PORTA_EN_LOW_INDEX, ®_value_l))
00120 {
00121 TRACE( "V1495 PORT A enable write failed !\n");
00122 return FALSE;
00123 }
00124 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_PORTA_EN_HIGH_INDEX, ®_value_h))
00125 {
00126 TRACE( "V1495 PORT A enable write failed !\n");
00127 return FALSE;
00128 }
00129 return TRUE;
00130 }
00131
00133
00135 BOOL cvt_V1495_set_port_B_enable( cvt_V1495_data* p_data, UINT32 value)
00136 {
00137 UINT16 reg_value_l= (UINT16)( value& 0xffff);
00138 UINT16 reg_value_h= (UINT16)( ((UINT32)value>>16)& 0xffff);
00139
00140 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_PORTB_EN_LOW_INDEX, ®_value_l))
00141 {
00142 TRACE( "V1495 PORT B enable write failed !\n");
00143 return FALSE;
00144 }
00145 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_PORTB_EN_HIGH_INDEX, ®_value_h))
00146 {
00147 TRACE( "V1495 PORT B enable write failed !\n");
00148 return FALSE;
00149 }
00150 return TRUE;
00151 }
00152
00154
00156 BOOL cvt_V1495_set_port_D_enable( cvt_V1495_data* p_data, UINT32 value)
00157 {
00158 UINT16 reg_value_l= (UINT16)( value& 0xffff);
00159 UINT16 reg_value_h= (UINT16)( ((UINT32)value>>16)& 0xffff);
00160
00161 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_PORTD_EN_LOW_INDEX, ®_value_l))
00162 {
00163 TRACE( "V1495 PORT D enable write failed !\n");
00164 return FALSE;
00165 }
00166 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1495_PORTD_EN_HIGH_INDEX, ®_value_h))
00167 {
00168 TRACE( "V1495 PORT D enable write failed !\n");
00169 return FALSE;
00170 }
00171 return TRUE;
00172 }
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