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00015 #include <memory.h>
00016 #include <string.h>
00017 #include "cvt_V792.h"
00018
00020
00022
00024
00026 #define V792_DATA_TYPE_MSK 0x07000000
00028 #define V792_HEADER 0x02000000
00029 #define V792_EOB 0x04000000
00030 #define V792_DATUM 0x00000000
00031 #define V792_NOT_VALID_DATUM 0x06000000
00033 #define IS_HEADER(data) ((data& V792_DATA_TYPE_MSK)== V792_HEADER)
00034 #define IS_EOB(data) ((data& V792_DATA_TYPE_MSK)== V792_EOB)
00035 #define IS_DATUM(data) ((data& V792_DATA_TYPE_MSK)== V792_DATUM)
00036 #define IS_NOT_VALID_DATUM(data) ((data& V792_DATA_TYPE_MSK)== V792_NOT_VALID_DATUM)
00038 #define GET_CH_COUNT(data) ((UINT32)((((UINT32)data)>> 8)& 0x0000003f))
00039 #define GET_EVENT_COUNT(data) ((UINT32)(((UINT32)data)& 0x00ffffff))
00041
00042 // Static variables declaration
00043
00044
00046
00051
00052 static const cvt_reg_table CVT_V792_REG_TABLE[]=
00053 {
00054 {CVT_V792_OUT_BUFFER_ADD, CVT_V792_OUT_BUFFER_AM, CVT_V792_OUT_BUFFER_DATA_SIZE},
00055 {CVT_V792_FW_REV_ADD, CVT_V792_FW_REV_AM, CVT_V792_FW_REV_DATA_SIZE},
00056 {CVT_V792_GEO_ADDRESS_ADD, CVT_V792_GEO_ADDRESS_AM, CVT_V792_GEO_ADDRESS_DATA_SIZE},
00057 {CVT_V792_MCST_CBLT_ADDRESS_ADD, CVT_V792_MCST_CBLT_ADDRESS_AM, CVT_V792_MCST_CBLT_ADDRESS_DATA_SIZE},
00058 {CVT_V792_BIT_SET_1_ADD, CVT_V792_BIT_SET_1_AM, CVT_V792_BIT_SET_1_DATA_SIZE},
00059 {CVT_V792_BIT_CLEAR_1_ADD, CVT_V792_BIT_CLEAR_1_AM, CVT_V792_BIT_CLEAR_1_DATA_SIZE},
00060 {CVT_V792_INT_LEVEL_ADD, CVT_V792_INT_LEVEL_AM, CVT_V792_INT_LEVEL_DATA_SIZE},
00061 {CVT_V792_INT_VECTOR_ADD, CVT_V792_INT_VECTOR_AM, CVT_V792_INT_VECTOR_DATA_SIZE},
00062 {CVT_V792_STATUS_1_ADD, CVT_V792_STATUS_1_AM, CVT_V792_STATUS_1_DATA_SIZE},
00063 {CVT_V792_CONTROL_1_ADD, CVT_V792_CONTROL_1_AM, CVT_V792_CONTROL_1_DATA_SIZE},
00064 {CVT_V792_ADER_HIGH_ADD, CVT_V792_ADER_HIGH_AM, CVT_V792_ADER_HIGH_DATA_SIZE},
00065 {CVT_V792_ADER_LOW_ADD, CVT_V792_ADER_LOW_AM, CVT_V792_ADER_LOW_DATA_SIZE},
00066 {CVT_V792_SINGLE_SHOT_RESET_ADD, CVT_V792_SINGLE_SHOT_RESET_AM, CVT_V792_SINGLE_SHOT_RESET_DATA_SIZE},
00067 {CVT_V792_MCST_CBLT_CTRL_ADD, CVT_V792_MCST_CBLT_CTRL_AM, CVT_V792_MCST_CBLT_CTRL_DATA_SIZE},
00068 {CVT_V792_EVENT_TRG_ADD, CVT_V792_EVENT_TRG_AM, CVT_V792_EVENT_TRG_DATA_SIZE},
00069 {CVT_V792_STATUS_2_ADD, CVT_V792_STATUS_2_AM, CVT_V792_STATUS_2_DATA_SIZE},
00070 {CVT_V792_EVENT_COUNTER_LOW_ADD, CVT_V792_EVENT_COUNTER_LOW_AM, CVT_V792_EVENT_COUNTER_LOW_DATA_SIZE},
00071 {CVT_V792_EVENT_COUNTER_HIGH_ADD, CVT_V792_EVENT_COUNTER_HIGH_AM, CVT_V792_EVENT_COUNTER_HIGH_DATA_SIZE},
00072 {CVT_V792_INC_EVENT_ADD, CVT_V792_INC_EVENT_AM, CVT_V792_INC_EVENT_DATA_SIZE},
00073 {CVT_V792_INC_OFFSET_ADD, CVT_V792_INC_OFFSET_AM, CVT_V792_INC_OFFSET_DATA_SIZE},
00074 {CVT_V792_LOAD_TEST_ADD, CVT_V792_LOAD_TEST_AM, CVT_V792_LOAD_TEST_DATA_SIZE},
00075 {CVT_V792_FCLR_WND_ADD, CVT_V792_FCLR_WND_AM, CVT_V792_FCLR_WND_DATA_SIZE},
00076 {CVT_V792_BIT_SET_2_ADD, CVT_V792_BIT_SET_2_AM, CVT_V792_BIT_SET_2_DATA_SIZE},
00077 {CVT_V792_BIT_CLEAR_2_ADD, CVT_V792_BIT_CLEAR_2_AM, CVT_V792_BIT_CLEAR_2_DATA_SIZE},
00078 {CVT_V792_W_MEMORY_TEST_ADDRESS_ADD,CVT_V792_W_MEMORY_TEST_ADDRESS_AM, CVT_V792_W_MEMORY_TEST_ADDRESS_DATA_SIZE},
00079 {CVT_V792_MEMORY_TEST_WORD_HIGH_ADD,CVT_V792_MEMORY_TEST_WORD_HIGH_AM, CVT_V792_MEMORY_TEST_WORD_HIGH_DATA_SIZE},
00080 {CVT_V792_MEMORY_TEST_WORD_LOW_ADD, CVT_V792_MEMORY_TEST_WORD_LOW_AM, CVT_V792_MEMORY_TEST_WORD_LOW_DATA_SIZE},
00081 {CVT_V792_CRATE_SELECT_ADD, CVT_V792_CRATE_SELECT_AM, CVT_V792_CRATE_SELECT_DATA_SIZE},
00082 {CVT_V792_TEST_EVENT_WRITE_ADD, CVT_V792_TEST_EVENT_WRITE_AM, CVT_V792_TEST_EVENT_WRITE_DATA_SIZE},
00083 {CVT_V792_EVENT_COUNT_RESET_ADD, CVT_V792_EVENT_COUNT_RESET_AM, CVT_V792_EVENT_COUNT_RESET_DATA_SIZE},
00084 {CVT_V792_IPED_ADD, CVT_V792_IPED_AM, CVT_V792_IPED_DATA_SIZE},
00085 {CVT_V792_R_TEST_ADDRESS_ADD, CVT_V792_R_TEST_ADDRESS_AM, CVT_V792_R_TEST_ADDRESS_DATA_SIZE},
00086 {CVT_V792_SW_COMM_ADD, CVT_V792_SW_COMM_AM, CVT_V792_SW_COMM_DATA_SIZE},
00087 {CVT_V792_SLIDE_CONSTANT_ADD, CVT_V792_SLIDE_CONSTANT_AM, CVT_V792_SLIDE_CONSTANT_DATA_SIZE},
00088 {CVT_V792_AAD_ADD, CVT_V792_AAD_AM, CVT_V792_AAD_DATA_SIZE},
00089 {CVT_V792_BAD_ADD, CVT_V792_BAD_AM, CVT_V792_BAD_DATA_SIZE},
00090 {CVT_V792_THRESHOLD_0_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00091 {CVT_V792_THRESHOLD_1_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00092 {CVT_V792_THRESHOLD_2_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00093 {CVT_V792_THRESHOLD_3_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00094 {CVT_V792_THRESHOLD_4_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00095 {CVT_V792_THRESHOLD_5_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00096 {CVT_V792_THRESHOLD_6_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00097 {CVT_V792_THRESHOLD_7_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00098 {CVT_V792_THRESHOLD_8_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00099 {CVT_V792_THRESHOLD_9_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00100 {CVT_V792_THRESHOLD_10_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00101 {CVT_V792_THRESHOLD_11_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00102 {CVT_V792_THRESHOLD_12_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00103 {CVT_V792_THRESHOLD_13_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00104 {CVT_V792_THRESHOLD_14_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00105 {CVT_V792_THRESHOLD_15_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00106 {CVT_V792_THRESHOLD_16_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00107 {CVT_V792_THRESHOLD_17_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00108 {CVT_V792_THRESHOLD_18_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00109 {CVT_V792_THRESHOLD_19_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00110 {CVT_V792_THRESHOLD_20_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00111 {CVT_V792_THRESHOLD_21_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00112 {CVT_V792_THRESHOLD_22_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00113 {CVT_V792_THRESHOLD_23_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00114 {CVT_V792_THRESHOLD_24_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00115 {CVT_V792_THRESHOLD_25_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00116 {CVT_V792_THRESHOLD_26_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00117 {CVT_V792_THRESHOLD_27_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00118 {CVT_V792_THRESHOLD_28_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00119 {CVT_V792_THRESHOLD_29_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00120 {CVT_V792_THRESHOLD_30_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00121 {CVT_V792_THRESHOLD_31_ADD, CVT_V792_THRESHOLD_AM, CVT_V792_THRESHOLD_DATA_SIZE},
00122 {CVT_V792_ROM_OUI_MSB_ADD, CVT_V792_ROM_OUI_MSB_AM, CVT_V792_ROM_OUI_MSB_DATA_SIZE},
00123 {CVT_V792_ROM_OUI_ADD, CVT_V792_ROM_OUI_AM, CVT_V792_ROM_OUI_DATA_SIZE},
00124 {CVT_V792_ROM_OUI_LSB_ADD, CVT_V792_ROM_OUI_LSB_AM, CVT_V792_ROM_OUI_LSB_DATA_SIZE},
00125 {CVT_V792_ROM_VERSION_ADD, CVT_V792_ROM_VERSION_AM, CVT_V792_ROM_VERSION_DATA_SIZE},
00126 {CVT_V792_ROM_BOARD_ID_MSB_ADD, CVT_V792_ROM_BOARD_ID_MSB_AM, CVT_V792_ROM_BOARD_ID_MSB_DATA_SIZE},
00127 {CVT_V792_ROM_BOARD_ID_ADD, CVT_V792_ROM_BOARD_ID_AM, CVT_V792_ROM_BOARD_ID_DATA_SIZE},
00128 {CVT_V792_ROM_BOARD_ID_LSB_ADD, CVT_V792_ROM_BOARD_ID_LSB_AM, CVT_V792_ROM_BOARD_ID_LSB_DATA_SIZE},
00129 {CVT_V792_ROM_REVISION_ADD, CVT_V792_ROM_REVISION_AM, CVT_V792_ROM_REVISION_DATA_SIZE},
00130 {CVT_V792_ROM_SERIAL_MSB_ADD, CVT_V792_ROM_SERIAL_MSB_AM, CVT_V792_ROM_SERIAL_MSB_DATA_SIZE},
00131 {CVT_V792_ROM_SERIAL_LSB_ADD, CVT_V792_ROM_SERIAL_LSB_AM, CVT_V792_ROM_SERIAL_LSB_DATA_SIZE},
00132 };
00133
00135
00137
00139
00141
00143
00144
00145
00147
00149
00151 BOOL cvt_V792_open( cvt_V792_data* p_data, UINT16 base_address, long vme_handle, CVT_V792_TYPES type)
00152 {
00153 memset( p_data, 0, sizeof( cvt_V792_data));
00154
00155 switch( type)
00156 {
00157 case CVT_V792_TYPE_A:
00158 case CVT_V792_TYPE_N:
00159 break;
00160 default:
00161 TRACE1( "cvt_V792_open: bad board type: %d\n", type);
00162 return FALSE;
00163 }
00164
00165
00166 if( !cvt_board_open( &p_data->m_common_data, base_address, vme_handle, CVT_V792_REG_TABLE))
00167 return FALSE;
00168
00169 p_data->m_type= type;
00170 p_data->m_common_data.set_MCST_CBLT= cvt_V792_set_MCST_CBLT;
00171
00172 #ifdef CVT_V792_USE_DATA_QUEUE
00173 p_data->m_queue= malloc( CVT_V792_QUEUE_SIZE_DWORD* sizeof( UINT32));
00174 if( p_data->m_queue== NULL)
00175 {
00176 TRACE( "cvt_V792_open: cannot allocate queue buffer\n");
00177 return FALSE;
00178 }
00179 memset( p_data->m_queue, 0, CVT_V792_QUEUE_SIZE_DWORD* sizeof( UINT32));
00180 #endif
00181
00182 return TRUE;
00183 }
00184
00186
00188 BOOL cvt_V792_close( cvt_V792_data* p_data)
00189 {
00190 #ifdef CVT_V792_USE_DATA_QUEUE
00191 if( p_data->m_queue!= NULL)
00192 {
00193 free( p_data->m_queue);
00194 }
00195 #endif
00196 if( !cvt_board_close( &p_data->m_common_data))
00197 return FALSE;
00198 return TRUE;
00199 }
00200
00202
00203
00204
00206
00207
00209
00210
00211
00213
00215
00217 BOOL cvt_V792_set_geo_address( cvt_V792_data* p_data, UINT8 value)
00218 {
00219 UINT16 reg_value= value;
00220
00221 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_GEO_ADDRESS_INDEX, ®_value))
00222 {
00223 TRACE( "V792 CVT_V792_GEO_ADDRESS write failed !\n");
00224 return FALSE;
00225 }
00226 return TRUE;
00227 }
00228
00230
00232 BOOL cvt_V792_get_geo_address( cvt_V792_data* p_data, UINT8 *p_value)
00233 {
00234 UINT16 reg_value= 0;
00235
00236 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_GEO_ADDRESS_INDEX, ®_value))
00237 {
00238 TRACE( "V792 CVT_V792_GEO_ADDRESS read failed !\n");
00239 return FALSE;
00240 }
00241 *p_value= (UINT8)((UINT16)( reg_value& 0x1f));
00242 return TRUE;
00243 }
00244
00246
00248 BOOL cvt_V792_set_MCST_CBLT_address( cvt_V792_data* p_data, UINT8 value)
00249 {
00250 UINT16 reg_value= value;
00251
00252 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_MCST_CBLT_ADDRESS_INDEX, ®_value))
00253 {
00254 TRACE( "V792 CVT_V792_MCST_CBLT_ADDRESS write failed !\n");
00255 return FALSE;
00256 }
00257 return TRUE;
00258 }
00259
00261
00263 BOOL cvt_V792_get_MCST_CBLT_address( cvt_V792_data* p_data, UINT8 *p_value)
00264 {
00265 UINT16 reg_value= 0;
00266
00267 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_MCST_CBLT_ADDRESS_INDEX, ®_value))
00268 {
00269 TRACE( "V792 CVT_V792_GEO_ADDRESS read failed !\n");
00270 return FALSE;
00271 }
00272 *p_value= (UINT8)((UINT16)( reg_value& 0xff));
00273 return TRUE;
00274 }
00275
00277
00279 BOOL cvt_V792_set_bit_set_1( cvt_V792_data* p_data, UINT16 value)
00280 {
00281 UINT16 reg_value= value;
00282
00283 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_1_INDEX, ®_value))
00284 {
00285 TRACE( "V792 CVT_V792_BIT_SET_1 write failed !\n");
00286 return FALSE;
00287 }
00288 return TRUE;
00289 }
00290
00292
00294 BOOL cvt_V792_set_bit_clear_1( cvt_V792_data* p_data, UINT16 value)
00295 {
00296 UINT16 reg_value= value;
00297
00298 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_1_INDEX, ®_value))
00299 {
00300 TRACE( "V792 BIT_CLEAR_1 write failed !\n");
00301 return FALSE;
00302 }
00303 return TRUE;
00304 }
00305
00307
00309 BOOL cvt_V792_set_interrupt_level( cvt_V792_data* p_data, UINT8 value)
00310 {
00311 UINT16 reg_value= value;
00312
00313 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_INT_LEVEL_INDEX, ®_value))
00314 {
00315 TRACE( "V792 CVT_V792_INT_LEVEL write failed !\n");
00316 return FALSE;
00317 }
00318 return TRUE;
00319 }
00320
00322
00324 BOOL cvt_V792_get_interrupt_level( cvt_V792_data* p_data, UINT8 *p_value)
00325 {
00326 UINT16 reg_value= 0;
00327
00328 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_INT_LEVEL_INDEX, ®_value))
00329 {
00330 TRACE( "V792 CVT_V792_INT_LEVEL read failed !\n");
00331 return FALSE;
00332 }
00333 *p_value= (UINT8)((UINT16)( reg_value& 0x07));
00334 return TRUE;
00335 }
00336
00338
00340 BOOL cvt_V792_set_interrupt_vector( cvt_V792_data* p_data, UINT8 value)
00341 {
00342 UINT16 reg_value= value;
00343
00344 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_INT_VECTOR_INDEX, ®_value))
00345 {
00346 TRACE( "V792 CVT_V792_INT_VECTOR write failed !\n");
00347 return FALSE;
00348 }
00349 return TRUE;
00350 }
00351
00353
00355 BOOL cvt_V792_get_interrupt_vector( cvt_V792_data* p_data, UINT8 *p_value)
00356 {
00357 UINT16 reg_value= 0;
00358
00359 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_INT_VECTOR_INDEX, ®_value))
00360 {
00361 TRACE( "V792 CVT_V792_INT_VECTOR read failed !\n");
00362 return FALSE;
00363 }
00364 *p_value= (UINT8)((UINT16)( reg_value& 0xff));
00365 return TRUE;
00366 }
00367
00369
00371 BOOL cvt_V792_get_status_1( cvt_V792_data* p_data, UINT16* p_value)
00372 {
00373 UINT16 reg_value= 0;
00374
00375 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_STATUS_1_INDEX, ®_value))
00376 {
00377 TRACE( "V792 CVT_V792_STATUS_1 read failed !\n");
00378 return FALSE;
00379 }
00380 *p_value= reg_value;
00381 return TRUE;
00382 }
00383
00385
00387 BOOL cvt_V792_set_control_1( cvt_V792_data* p_data, UINT16 value)
00388 {
00389 UINT16 reg_value= value;
00390
00391 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_CONTROL_1_INDEX, ®_value))
00392 {
00393 TRACE( "V792 CVT_V792_CONTROL_1 write failed !\n");
00394 return FALSE;
00395 }
00396 return TRUE;
00397 }
00398
00400
00402 BOOL cvt_V792_get_control_1( cvt_V792_data* p_data, UINT16* p_value)
00403 {
00404 UINT16 reg_value= 0;
00405
00406 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_CONTROL_1_INDEX, ®_value))
00407 {
00408 TRACE( "V792 CVT_V792_CONTROL_1 read failed !\n");
00409 return FALSE;
00410 }
00411 *p_value= reg_value;
00412 return TRUE;
00413 }
00414
00416
00418 BOOL cvt_V792_set_bitmask_control_1( cvt_V792_data* p_data, CVT_V792_CONTROL_1_MSK value)
00419 {
00420 UINT16 reg_value= value;
00421
00422 if( !cvt_set_bitmask( &p_data->m_common_data, CVT_V792_CONTROL_1_ADD, ®_value, CVT_V792_CONTROL_1_AM, CVT_V792_CONTROL_1_DATA_SIZE))
00423 {
00424 TRACE( "V792 CVT_V792_CONTROL_1_SET failed !\n");
00425 return FALSE;
00426 }
00427 return TRUE;
00428 }
00429
00431
00433 BOOL cvt_V792_clear_bitmask_control_1( cvt_V792_data* p_data, CVT_V792_CONTROL_1_MSK value)
00434 {
00435 UINT16 reg_value= value;
00436
00437 if( !cvt_clear_bitmask( &p_data->m_common_data, CVT_V792_CONTROL_1_ADD, ®_value, CVT_V792_CONTROL_1_AM, CVT_V792_CONTROL_1_DATA_SIZE))
00438 {
00439 TRACE( "V792 CVT_V792_CONTROL_1_CLEAR failed !\n");
00440 return FALSE;
00441 }
00442 return TRUE;
00443 }
00444
00446
00448 BOOL cvt_V792_set_ader_high( cvt_V792_data* p_data, UINT8 value)
00449 {
00450 UINT16 reg_value= value;
00451
00452 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_ADER_HIGH_INDEX, ®_value))
00453 {
00454 TRACE( "V792 CVT_V792_ADER_HIGH write failed !\n");
00455 return FALSE;
00456 }
00457 return TRUE;
00458 }
00459
00461
00463 BOOL cvt_V792_get_ader_high( cvt_V792_data* p_data, UINT8 *p_value)
00464 {
00465 UINT16 reg_value= 0;
00466
00467 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_ADER_HIGH_INDEX, ®_value))
00468 {
00469 TRACE( "V792 CVT_V792_ADER_HIGH read failed !\n");
00470 return FALSE;
00471 }
00472 *p_value= (UINT8)((UINT16)( reg_value& 0xff));
00473 return TRUE;
00474 }
00475
00477
00479 BOOL cvt_V792_set_ader_low( cvt_V792_data* p_data, UINT8 value)
00480 {
00481 UINT16 reg_value= value;
00482
00483 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_ADER_LOW_INDEX, ®_value))
00484 {
00485 TRACE( "V792 CVT_V792_ADER_LOW write failed !\n");
00486 return FALSE;
00487 }
00488 return TRUE;
00489 }
00490
00492
00494 BOOL cvt_V792_get_ader_low( cvt_V792_data* p_data, UINT8 *p_value)
00495 {
00496 UINT16 reg_value= 0;
00497
00498 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_ADER_LOW_INDEX, ®_value))
00499 {
00500 TRACE( "V792 CVT_V792_ADER_LOW read failed !\n");
00501 return FALSE;
00502 }
00503 *p_value= (UINT8)((UINT16)( reg_value& 0xff));
00504 return TRUE;
00505 }
00506
00508
00510 BOOL cvt_V792_single_shot_reset( cvt_V792_data* p_data)
00511 {
00512 UINT16 reg_value= 0;
00513
00514 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_SINGLE_SHOT_RESET_INDEX, ®_value))
00515 {
00516 TRACE( "V792 CVT_V792_SINGLE_SHOT_RESET write failed !\n");
00517 return FALSE;
00518 }
00519 return TRUE;
00520 }
00521
00523
00525 BOOL cvt_V792_set_MCST_CBLT_control( cvt_V792_data* p_data, UINT8 value)
00526 {
00527 UINT16 reg_value= value;
00528
00529 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_MCST_CBLT_CTRL_INDEX, ®_value))
00530 {
00531 TRACE( "V792 CVT_V792_MCST_CBLT_CTRL write failed !\n");
00532 return FALSE;
00533 }
00534 return TRUE;
00535 }
00536
00538
00540 BOOL cvt_V792_get_MCST_CBLT_control( cvt_V792_data* p_data, UINT8 *p_value)
00541 {
00542 UINT16 reg_value= 0;
00543
00544 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_MCST_CBLT_CTRL_INDEX, ®_value))
00545 {
00546 TRACE( "V792 CVT_V792_MCST_CBLT_CTRL read failed !\n");
00547 return FALSE;
00548 }
00549 *p_value= (UINT8)((UINT16)( reg_value& 0x03));
00550 return TRUE;
00551 }
00552
00554
00556 BOOL cvt_V792_set_event_trigger( cvt_V792_data* p_data, UINT8 value)
00557 {
00558 UINT16 reg_value= value;
00559
00560 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_EVENT_TRG_INDEX, ®_value))
00561 {
00562 TRACE( "V792 CVT_V792_EVENT_TRG write failed !\n");
00563 return FALSE;
00564 }
00565 return TRUE;
00566 }
00567
00569
00571 BOOL cvt_V792_get_event_trigger( cvt_V792_data* p_data, UINT8 *p_value)
00572 {
00573 UINT16 reg_value= 0;
00574
00575 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_EVENT_TRG_INDEX, ®_value))
00576 {
00577 TRACE( "V792 CVT_V792_EVENT_TRG read failed !\n");
00578 return FALSE;
00579 }
00580 *p_value= (UINT8)((UINT16)( reg_value& 0x1f));
00581 return TRUE;
00582 }
00583
00585
00587 BOOL cvt_V792_get_status_2( cvt_V792_data* p_data, UINT16* p_value)
00588 {
00589 UINT16 reg_value= 0;
00590
00591 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_STATUS_2_INDEX, ®_value))
00592 {
00593 TRACE( "V792 CVT_V792_STATUS_2 read failed !\n");
00594 return FALSE;
00595 }
00596 *p_value= reg_value;
00597 return TRUE;
00598 }
00599
00600
00602
00604 BOOL cvt_V792_set_threshold( cvt_V792_data* p_data, cvt_V792_threshold_id threshold_id, UINT16 value)
00605 {
00606 UINT16 reg_value= value;
00607 int max_thresholds= 0;
00608 switch( p_data->m_type)
00609 {
00610 case CVT_V792_TYPE_A:
00611 max_thresholds= CVT_V792_MAX_THRESHOLD_A;
00612 break;
00613 case CVT_V792_TYPE_N:
00614 max_thresholds= CVT_V792_MAX_THRESHOLD_N;
00615 break;
00616 default:
00617 TRACE1( "cvt_V792_set_threshold: bad board type: %d\n", p_data->m_type);
00618 return FALSE;
00619 }
00620
00621
00622 switch( threshold_id)
00623 {
00624 case CVT_V792_THRESHOLD_ALL:
00625 {
00626
00627 int i;
00628 for( i= CVT_V792_THRESHOLD_0; i< max_thresholds; i++)
00629 {
00630 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ (i- CVT_V792_THRESHOLD_0), ®_value))
00631 {
00632 TRACE1( "V792 THRESHOLD %i write failed !\n", i- CVT_V792_THRESHOLD_0);
00633 return FALSE;
00634 }
00635 }
00636 }
00637 break;
00638 case CVT_V792_THRESHOLD_0:
00639 case CVT_V792_THRESHOLD_1:
00640 case CVT_V792_THRESHOLD_2:
00641 case CVT_V792_THRESHOLD_3:
00642 case CVT_V792_THRESHOLD_4:
00643 case CVT_V792_THRESHOLD_5:
00644 case CVT_V792_THRESHOLD_6:
00645 case CVT_V792_THRESHOLD_7:
00646 case CVT_V792_THRESHOLD_8:
00647 case CVT_V792_THRESHOLD_9:
00648 case CVT_V792_THRESHOLD_10:
00649 case CVT_V792_THRESHOLD_11:
00650 case CVT_V792_THRESHOLD_12:
00651 case CVT_V792_THRESHOLD_13:
00652 case CVT_V792_THRESHOLD_14:
00653 case CVT_V792_THRESHOLD_15:
00654 case CVT_V792_THRESHOLD_16:
00655 case CVT_V792_THRESHOLD_17:
00656 case CVT_V792_THRESHOLD_18:
00657 case CVT_V792_THRESHOLD_19:
00658 case CVT_V792_THRESHOLD_20:
00659 case CVT_V792_THRESHOLD_21:
00660 case CVT_V792_THRESHOLD_22:
00661 case CVT_V792_THRESHOLD_23:
00662 case CVT_V792_THRESHOLD_24:
00663 case CVT_V792_THRESHOLD_25:
00664 case CVT_V792_THRESHOLD_26:
00665 case CVT_V792_THRESHOLD_27:
00666 case CVT_V792_THRESHOLD_28:
00667 case CVT_V792_THRESHOLD_29:
00668 case CVT_V792_THRESHOLD_30:
00669 case CVT_V792_THRESHOLD_31:
00670 if( threshold_id>= max_thresholds)
00671 return FALSE;
00672
00673 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ ( threshold_id- CVT_V792_THRESHOLD_0), ®_value))
00674 {
00675 TRACE1( "V792 THRESHOLD %i write failed !\n", threshold_id- CVT_V792_THRESHOLD_0);
00676 return FALSE;
00677 }
00678 default:
00679 TRACE1( "V792 Unhandled threshold id %i !\n", threshold_id);
00680 return FALSE;
00681 }
00682 return TRUE;
00683 }
00684
00686
00688 BOOL cvt_V792_set_bit_set_2( cvt_V792_data* p_data, UINT16 value)
00689 {
00690 UINT16 reg_value= value;
00691
00692 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00693 {
00694 TRACE( "V792 CVT_V792_BIT_SET_2 write failed !\n");
00695 return FALSE;
00696 }
00697 return TRUE;
00698 }
00699
00701
00703 BOOL cvt_V792_set_bit_clear_2( cvt_V792_data* p_data, UINT16 value)
00704 {
00705 UINT16 reg_value= value;
00706
00707 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00708 {
00709 TRACE( "V792 BIT_CLEAR_2 write failed !\n");
00710 return FALSE;
00711 }
00712 return TRUE;
00713 }
00714
00716
00717
00718
00720
00722
00724 BOOL cvt_V792_set_sliding_scale( cvt_V792_data* p_data, BOOL enable, UINT8 sliding_constant)
00725 {
00726 UINT16 reg_value;
00727 if( !enable)
00728 {
00729
00730 reg_value= sliding_constant;
00731 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_SLIDE_CONSTANT_INDEX, ®_value))
00732 {
00733 TRACE( "V792 CVT_V792_SLIDE_CONSTANT write failed !\n");
00734 return FALSE;
00735 }
00736
00737 reg_value= CVT_V792_BSC2_SLIDE_EN_MSK;
00738 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00739 {
00740 TRACE( "V792 CVT_V792_BSC2_SLIDE_EN_MSK bit clear failed !\n");
00741 return FALSE;
00742 }
00743 }
00744 else
00745 {
00746
00747 reg_value= CVT_V792_BSC2_SLIDE_EN_MSK;
00748 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00749 {
00750 TRACE( "V792 CVT_V792_BSC2_SLIDE_EN_MSK bit set failed !\n");
00751 return FALSE;
00752 }
00753
00754 }
00755 return TRUE;
00756 }
00757
00759
00761 BOOL cvt_V792_set_zero_suppression( cvt_V792_data* p_data, BOOL enable, BOOL step_threshold, const UINT16* thresholds_buff)
00762 {
00763 UINT16 reg_value;
00764 if( !enable)
00765 {
00766
00767 reg_value= CVT_V792_BSC2_LOW_THR_DIS_MSK;
00768 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00769 {
00770 TRACE( "V792 CVT_V792_BSC2_LOW_THR_DIS_MSK bit set failed !\n");
00771 return FALSE;
00772 }
00773 }
00774 else
00775 {
00776
00777 reg_value= CVT_V792_BSC2_LOW_THR_DIS_MSK;
00778 if( thresholds_buff!= NULL)
00779 {
00780 int i;
00781 int max_thresholds= 0;
00782 switch( p_data->m_type)
00783 {
00784 case CVT_V792_TYPE_A:
00785 max_thresholds= CVT_V792_MAX_THRESHOLD_A;
00786 break;
00787 case CVT_V792_TYPE_N:
00788 max_thresholds= CVT_V792_MAX_THRESHOLD_N;
00789 break;
00790 default:
00791 TRACE1( "cvt_V792_set_zero_suppression: bad board type: %d\n", p_data->m_type);
00792 return FALSE;
00793 }
00794
00795 for( i= CVT_V792_THRESHOLD_0; i< max_thresholds; i++)
00796 {
00797 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ (i- CVT_V792_THRESHOLD_0), thresholds_buff++))
00798 {
00799 TRACE1( "V792 THRESHOLD %i write failed !\n", i- CVT_V792_THRESHOLD_0);
00800 return FALSE;
00801 }
00802 }
00803 }
00804
00805
00806 reg_value= CVT_V792_BSC2_STEP_TH_MSK;
00807 if( step_threshold)
00808 {
00809 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00810 {
00811 TRACE( "V792 CVT_V792_BSC2_STEP_TH_MSK bit set failed !\n");
00812 return FALSE;
00813 }
00814 }
00815 else
00816 {
00817 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00818 {
00819 TRACE( "V792 CVT_V792_BSC2_STEP_TH_MSK bit clear failed !\n");
00820 return FALSE;
00821 }
00822 }
00823
00824
00825 reg_value= CVT_V792_BSC2_LOW_THR_DIS_MSK;
00826 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00827 {
00828 TRACE( "V792 CVT_V792_BSC2_LOW_THR_DIS_MSK bit clear failed !\n");
00829 return FALSE;
00830 }
00831 }
00832 return TRUE;
00833 }
00834
00836
00838 BOOL cvt_V792_set_overflow_suppression( cvt_V792_data* p_data, BOOL enable)
00839 {
00840 UINT16 reg_value;
00841
00842
00843 reg_value= CVT_V792_BSC2_OVER_RANGE_DIS_MSK;
00844 if( !enable)
00845 {
00846
00847 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00848 {
00849 TRACE( "V792 CVT_V792_BSC2_OVER_RANGE_DIS_MSK bit set failed !\n");
00850 return FALSE;
00851 }
00852 }
00853 else
00854 {
00855
00856 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00857 {
00858 TRACE( "V792 CVT_V792_BSC2_OVER_RANGE_DIS_MSK bit clear failed !\n");
00859 return FALSE;
00860 }
00861 }
00862 return TRUE;
00863 }
00864
00866
00868 BOOL cvt_V792_set_MEB( cvt_V792_data* p_data, BOOL empty_enable, BOOL auto_incr_enable)
00869 {
00870 UINT16 reg_value;
00871
00872
00873 reg_value= CVT_V792_BSC2_EMPTY_EN_MSK;
00874 if( !empty_enable)
00875 {
00876
00877 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00878 {
00879 TRACE( "V792 CVT_V792_BSC2_EMPTY_EN_MSK bit clear failed !\n");
00880 return FALSE;
00881 }
00882 }
00883 else
00884 {
00885
00886 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00887 {
00888 TRACE( "V792 CVT_V792_BSC2_EMPTY_EN_MSK bit set failed !\n");
00889 return FALSE;
00890 }
00891 }
00892
00893 reg_value= CVT_V792_BSC2_AUTO_INC_MSK;
00894 if( !auto_incr_enable)
00895 {
00896
00897 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00898 {
00899 TRACE( "V792 CVT_V792_BSC2_AUTO_INC_MSK bit clear failed !\n");
00900 return FALSE;
00901 }
00902 }
00903 else
00904 {
00905
00906 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00907 {
00908 TRACE( "V792 CVT_V792_BSC2_AUTO_INC_MSK bit set failed !\n");
00909 return FALSE;
00910 }
00911 }
00912 return TRUE;
00913 }
00914
00916
00918 BOOL cvt_V792_set_event_counter( cvt_V792_data* p_data, BOOL count_all_events, BOOL reset_count)
00919 {
00920 UINT16 reg_value;
00921
00922
00923 reg_value= CVT_V792_BSC2_ALL_TRG_MSK;
00924 if( !count_all_events)
00925 {
00926
00927 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
00928 {
00929 TRACE( "V792 CVT_V792_BSC2_ALL_TRG_MSK bit clear failed !\n");
00930 return FALSE;
00931 }
00932 }
00933 else
00934 {
00935
00936 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
00937 {
00938 TRACE( "V792 CVT_V792_BSC2_ALL_TRG_MSK bit set failed !\n");
00939 return FALSE;
00940 }
00941 }
00942
00943
00944 reg_value= 0;
00945 if( reset_count)
00946 {
00947
00948 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_EVENT_COUNT_RESET_INDEX, ®_value))
00949 {
00950 TRACE( "V792 CVT_V792_EVENT_COUNT_RESET write failed !\n");
00951 return FALSE;
00952 }
00953 }
00954 return TRUE;
00955 }
00956
00958
00960 BOOL cvt_V792_read_MEB( cvt_V792_data* p_data, void* p_buff, UINT32* p_buff_size)
00961 {
00962 if( !cvt_FIFO_BLT_read( &p_data->m_common_data, CVT_V792_OUT_BUFFER_ADD, p_buff, *p_buff_size, p_buff_size, CVT_V792_OUT_BUFFER_AM, CVT_V792_OUT_BUFFER_DATA_SIZE))
00963 {
00964 return FALSE;
00965 }
00966
00967 if( *p_buff_size== sizeof( UINT32))
00968 {
00969 if( IS_NOT_VALID_DATUM( *((UINT32*)p_buff)))
00970 *p_buff_size= 0;
00971 }
00972 return TRUE;
00973 }
00974
00976
00978 BOOL cvt_V792_set_fast_clear_window( cvt_V792_data* p_data, UINT16 value)
00979 {
00980 UINT16 reg_value= value;
00981
00982 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_FCLR_WND_INDEX, ®_value))
00983 {
00984 TRACE( "V792 CVT_V792_FCLR_WND write failed !\n");
00985 return FALSE;
00986 }
00987 return TRUE;
00988 }
00989
00991
00993 BOOL cvt_V792_set_acquisition_mode( cvt_V792_data* p_data, BOOL sliding_scale_enable, BOOL zero_suppression_enable, BOOL overflow_suppression_enable, BOOL empty_enable, BOOL count_all_events)
00994 {
00995 UINT16 set_msk= 0;
00996 UINT16 clear_msk= 0;
00997
00998
00999
01000 set_msk|= ( sliding_scale_enable)? CVT_V792_BSC2_SLIDE_EN_MSK: 0;
01001 clear_msk|= ( sliding_scale_enable)? 0: CVT_V792_BSC2_SLIDE_EN_MSK;
01002
01003
01004 set_msk|= ( zero_suppression_enable)? 0: CVT_V792_BSC2_LOW_THR_DIS_MSK;
01005 clear_msk|= ( zero_suppression_enable)? CVT_V792_BSC2_LOW_THR_DIS_MSK: 0;
01006
01007
01008 set_msk|= ( overflow_suppression_enable)? 0: CVT_V792_BSC2_OVER_RANGE_DIS_MSK;
01009 clear_msk|= ( overflow_suppression_enable)? CVT_V792_BSC2_OVER_RANGE_DIS_MSK: 0;
01010
01011
01012 set_msk|= ( empty_enable)? CVT_V792_BSC2_EMPTY_EN_MSK: 0;
01013 clear_msk|= ( empty_enable)? 0: CVT_V792_BSC2_EMPTY_EN_MSK;
01014
01015
01016 set_msk|= ( count_all_events)? CVT_V792_BSC2_ALL_TRG_MSK: 0;
01017 clear_msk|= ( count_all_events)? 0: CVT_V792_BSC2_ALL_TRG_MSK;
01018
01019
01020
01021 if( set_msk)
01022 {
01023 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, &set_msk))
01024 {
01025 TRACE( "V792 CVT_V792_BIT_SET_2 write failed !\n");
01026 return FALSE;
01027 }
01028 }
01029
01030
01031 if( clear_msk)
01032 {
01033
01034 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, &clear_msk))
01035 {
01036 TRACE( "V792 CVT_V792_BIT_CLEAR_2 write failed !\n");
01037 return FALSE;
01038 }
01039 }
01040 return TRUE;
01041 }
01043
01045 BOOL cvt_V792_set_interrupt( cvt_V792_data* p_data, UINT8 level, UINT8 vector, UINT8 event_number)
01046 {
01047 UINT16 reg_value;
01048
01049
01050 reg_value= level& 0x07;
01051 if( level!= reg_value)
01052 {
01053 TRACE( "V792 bad interrupt level !\n");
01054 return FALSE;
01055 }
01056 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_INT_LEVEL_INDEX, ®_value))
01057 {
01058 TRACE( "V792 CVT_V792_INT_LEVEL write failed !\n");
01059 return FALSE;
01060 }
01061
01062
01063 reg_value= vector;
01064 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_INT_VECTOR_INDEX, ®_value))
01065 {
01066 TRACE( "V792 CVT_V792_INT_VECTOR write failed !\n");
01067 return FALSE;
01068 }
01069
01070
01071 reg_value= event_number& 0x1f;
01072 if( event_number!= reg_value)
01073 {
01074 TRACE( "V792 bad interrupt event number !\n");
01075 return FALSE;
01076 }
01077 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_EVENT_TRG_INDEX, ®_value))
01078 {
01079 TRACE( "V792 CVT_V792_EVENT_TRG write failed !\n");
01080 return FALSE;
01081 }
01082 return TRUE;
01083 }
01084
01086
01088 BOOL cvt_V792_set_readout_mode( cvt_V792_data* p_data, BOOL bus_error_enable, BOOL block_end_enable, BOOL align64_enable)
01089 {
01090 UINT16 set_msk= 0;
01091 UINT16 clear_msk= 0;
01092
01093
01094
01095 set_msk|= ( bus_error_enable)? CVT_V792_CTRL1_BERR_ENABLE_MSK: 0;
01096 clear_msk|= ( bus_error_enable)? 0: CVT_V792_CTRL1_BERR_ENABLE_MSK;
01097
01098
01099 set_msk|= ( block_end_enable)? CVT_V792_CTRL1_BLKEND_MSK: 0;
01100 clear_msk|= ( block_end_enable)? 0: CVT_V792_CTRL1_BLKEND_MSK;
01101
01102
01103 set_msk|= ( align64_enable)? CVT_V792_CTRL1_ALIGN64_MSK: 0;
01104 clear_msk|= ( align64_enable)? 0: CVT_V792_CTRL1_ALIGN64_MSK;
01105
01106
01107
01108 if( set_msk)
01109 {
01110 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V792_CONTROL_1_INDEX, &set_msk))
01111 {
01112 TRACE( "V792 CVT_V792_CONTROL_1 write failed !\n");
01113 return FALSE;
01114 }
01115 }
01116
01117
01118 if( clear_msk)
01119 {
01120
01121 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V792_CONTROL_1_INDEX, &clear_msk))
01122 {
01123 TRACE( "V792 CVT_V792_CONTROL_1 write failed !\n");
01124 return FALSE;
01125 }
01126 }
01127 return TRUE;
01128 }
01130
01132 BOOL cvt_V792_get_status( cvt_V792_data* p_data, BOOL *p_is_data_ready, BOOL *p_is_busy, BOOL *p_is_term_on, BOOL *p_is_buffer_full)
01133 {
01134 UINT16 reg_value= 0;
01135
01136
01137 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_STATUS_1_INDEX, ®_value))
01138 {
01139 TRACE( "V792 CVT_V792_STATUS_1 read failed !\n");
01140 return FALSE;
01141 }
01142 *p_is_data_ready= ( reg_value& CVT_V792_STS1_DREADY_MSK)? TRUE: FALSE;
01143 *p_is_busy= ( reg_value& CVT_V792_STS1_BUSY_MSK)? TRUE: FALSE;
01144 *p_is_term_on= ( reg_value& CVT_V792_STS1_TERM_ON_MSK)? TRUE: FALSE;
01145
01146
01147 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_STATUS_2_INDEX, ®_value))
01148 {
01149 TRACE( "V792 CVT_V792_STATUS_2 read failed !\n");
01150 return FALSE;
01151 }
01152 *p_is_buffer_full= ( reg_value& CVT_V792_STS2_BUFFER_FULL_MSK)? TRUE: FALSE;
01153
01154 return TRUE;
01155 }
01156
01158
01160 BOOL cvt_V792_set_thresholds( cvt_V792_data* p_data, BOOL step_threshold, const UINT8* thresholds_value_buff)
01161 {
01162 UINT16 reg_value;
01163
01164
01165 if( thresholds_value_buff!= NULL)
01166 {
01167 int i;
01168 int max_thresholds= 0;
01169 switch( p_data->m_type)
01170 {
01171 case CVT_V792_TYPE_A:
01172 max_thresholds= CVT_V792_MAX_THRESHOLD_A;
01173 break;
01174 case CVT_V792_TYPE_N:
01175 max_thresholds= CVT_V792_MAX_THRESHOLD_N;
01176 break;
01177 default:
01178 TRACE1( "cvt_V792_set_thresholds: bad board type: %d\n", p_data->m_type);
01179 return FALSE;
01180 }
01181
01182 for( i= CVT_V792_THRESHOLD_0; i< max_thresholds; i++)
01183 {
01184 reg_value= CVT_V792_THRESHOLD_VALUE_MSK;
01185 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ (i- CVT_V792_THRESHOLD_0), ®_value))
01186 {
01187 TRACE1( "V792 THRESHOLD %i write failed !\n", i- CVT_V792_THRESHOLD_0);
01188 return FALSE;
01189 }
01190 reg_value= *(thresholds_value_buff++);
01191 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ (i- CVT_V792_THRESHOLD_0), ®_value))
01192 {
01193 TRACE1( "V792 THRESHOLD %i write failed !\n", i- CVT_V792_THRESHOLD_0);
01194 return FALSE;
01195 }
01196 }
01197 }
01198
01199
01200
01201 reg_value= CVT_V792_BSC2_STEP_TH_MSK;
01202 if( step_threshold)
01203 {
01204
01205 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
01206 {
01207 TRACE( "V792 CVT_V792_BSC2_STEP_TH_MSK bit set failed !\n");
01208 return FALSE;
01209 }
01210 }
01211 else
01212 {
01213
01214 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
01215 {
01216 TRACE( "V792 CVT_V792_BSC2_STEP_TH_MSK bit clear failed !\n");
01217 return FALSE;
01218 }
01219 }
01220
01221
01222
01223 reg_value= CVT_V792_BSC2_LOW_THR_DIS_MSK;
01224 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
01225 {
01226 TRACE( "V792 CVT_V792_BSC2_LOW_THR_DIS_MSK bit clear failed !\n");
01227 return FALSE;
01228 }
01229
01230 return TRUE;
01231 }
01232
01234
01236 BOOL cvt_V792_set_channel_enable( cvt_V792_data* p_data, UINT32 enable_msk)
01237 {
01238 UINT16 reg_value;
01239
01240
01241 int i;
01242 int max_thresholds= 0;
01243 switch( p_data->m_type)
01244 {
01245 case CVT_V792_TYPE_A:
01246 max_thresholds= CVT_V792_MAX_THRESHOLD_A;
01247 break;
01248 case CVT_V792_TYPE_N:
01249 max_thresholds= CVT_V792_MAX_THRESHOLD_N;
01250 break;
01251 default:
01252 TRACE1( "cvt_V792_set_channel_enable: bad board type: %d\n", p_data->m_type);
01253 return FALSE;
01254 }
01255
01256
01257 reg_value= CVT_V792_THRESHOLD_KILL_MSK;
01258 for( i= CVT_V792_THRESHOLD_0; i< max_thresholds; i++, enable_msk>>= 1)
01259 {
01260 if( enable_msk& 0x01)
01261 {
01262 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ (i- CVT_V792_THRESHOLD_0), ®_value))
01263 {
01264 TRACE1( "V792 THRESHOLD %i write failed !\n", i- CVT_V792_THRESHOLD_0);
01265 return FALSE;
01266 }
01267 }
01268 else
01269 {
01270 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V792_THRESHOLD_0_INDEX+ (i- CVT_V792_THRESHOLD_0), ®_value))
01271 {
01272 TRACE1( "V792 THRESHOLD %i write failed !\n", i- CVT_V792_THRESHOLD_0);
01273 return FALSE;
01274 }
01275 }
01276 }
01277 return TRUE;
01278 }
01279
01281
01283 BOOL cvt_V792_set_crate_number( cvt_V792_data* p_data, UINT8 crate_number)
01284 {
01285 UINT16 reg_value;
01286
01287
01288 reg_value= crate_number;
01289 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_CRATE_SELECT_INDEX, ®_value))
01290 {
01291 TRACE( "V792 CVT_V792_CRATE_SELECT write failed !\n");
01292 return FALSE;
01293 }
01294
01295 return TRUE;
01296 }
01297
01299
01301 BOOL cvt_V792_set_pedestal( cvt_V792_data* p_data, UINT8 value)
01302 {
01303 UINT16 reg_value= value;
01304
01305
01306 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_IPED_INDEX, ®_value))
01307 {
01308 TRACE( "V792 IPED write failed !\n");
01309 return FALSE;
01310 }
01311 return TRUE;
01312 }
01313
01315
01317 BOOL cvt_V792_get_event_counter( cvt_V792_data* p_data, UINT32* p_counter)
01318 {
01319 UINT16 reg_value;
01320 *p_counter= 0;
01321
01322 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_EVENT_COUNTER_LOW_INDEX, ®_value))
01323 {
01324 TRACE( "V792 CVT_V792_EVENT_COUNTER_LOW_INDEX read failed !\n");
01325 return FALSE;
01326 }
01327 *p_counter= reg_value;
01328
01329 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_EVENT_COUNTER_HIGH_INDEX, ®_value))
01330 {
01331 TRACE( "V792 CVT_V792_EVENT_COUNTER_HIGH_INDEX read failed !\n");
01332 return FALSE;
01333 }
01334 *p_counter|= ( ((UINT32)( reg_value& 0x00ff))<< 16);
01335
01336 return TRUE;
01337 }
01338
01340
01342 BOOL cvt_V792_get_system_info( cvt_V792_data* p_data, UINT16 *p_firmware_rev, UINT8 *p_piggy_back_type, UINT16 *p_serial_number)
01343 {
01344 UINT16 reg_value= 0;
01345
01346
01347 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_FW_REV_INDEX, ®_value))
01348 {
01349 TRACE( "V792 CVT_V792_FW_REV read failed !\n");
01350 return FALSE;
01351 }
01352 *p_firmware_rev= reg_value;
01353
01354
01355 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_STATUS_2_INDEX, ®_value))
01356 {
01357 TRACE( "V792 CVT_V792_STATUS_2 read failed !\n");
01358 return FALSE;
01359 }
01360 *p_piggy_back_type= CVT_V792_GET_PIGGY_BACK_TYPE( reg_value);
01361
01362
01363 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_ROM_SERIAL_LSB_INDEX, ®_value))
01364 {
01365 TRACE( "V792 CVT_V792_ROM_SERIAL_LSB read failed !\n");
01366 return FALSE;
01367 }
01368 *p_serial_number= reg_value& 0x00ff;
01369 if( !cvt_read_reg( &p_data->m_common_data, CVT_V792_ROM_SERIAL_MSB_INDEX, ®_value))
01370 {
01371 TRACE( "V792 CVT_V792_ROM_SERIAL_MSB read failed !\n");
01372 return FALSE;
01373 }
01374 *p_serial_number|= (reg_value& 0x00ff)<< 8;
01375
01376 return TRUE;
01377
01378 }
01379
01381
01383 BOOL cvt_V792_software_reset( cvt_V792_data* p_data)
01384 {
01385
01386
01387
01388
01389
01390
01391
01392
01393
01394
01395
01396
01397
01398
01399
01400
01401
01402 UINT16 reg_value= 0;
01403 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_SINGLE_SHOT_RESET_INDEX, ®_value))
01404 {
01405 TRACE( "V792 CVT_V792_SINGLE_SHOT_RESET write failed !\n");
01406 return FALSE;
01407 }
01408
01409 return TRUE;
01410 }
01411
01413
01415 BOOL cvt_V792_data_clear( cvt_V792_data* p_data)
01416 {
01417 UINT16 reg_value= (UINT16)CVT_V792_BSC2_CLEAR_DATA_MSK;
01418
01419 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_SET_2_INDEX, ®_value))
01420 {
01421 TRACE( "V792 SW_CLEAR write failed !\n");
01422 return FALSE;
01423 }
01424
01425 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_BIT_CLEAR_2_INDEX, ®_value))
01426 {
01427 TRACE( "V792 SW_CLEAR write failed !\n");
01428 return FALSE;
01429 }
01430
01431
01432
01433 reg_value= 0;
01434 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_EVENT_COUNT_RESET_INDEX, ®_value))
01435 {
01436 TRACE( "V792 CVT_V792_EVENT_COUNT_RESET write failed !\n");
01437 return FALSE;
01438 }
01439 return TRUE;
01440 }
01441
01442
01443 #ifdef CVT_V792_USE_DATA_QUEUE
01444
01445
01447 BOOL cvt_V792_peek_event( cvt_V792_data *p_data, UINT32 *out_buff, long *p_out_buff_size, UINT32 *p_event_count)
01448 {
01449 long in_org_pos= p_data->m_queue_ini;
01450 long out_org_pos= 0;
01451 int step= 0;
01452 UINT32 data;
01453 UINT32 found_count;
01454 long queue_ptr= in_org_pos;
01455 long out_buff_size= *p_out_buff_size;
01456 long num_word_to_read= 0;
01457 long delta_count;
01458
01459
01460 while( queue_ptr!= p_data->m_queue_end)
01461 {
01462 data= p_data->m_queue[ queue_ptr];
01463 if( ++queue_ptr>= CVT_V792_QUEUE_SIZE_DWORD)
01464 {
01465 queue_ptr= 0;
01466 }
01467 switch( step)
01468 {
01469 case 0:
01470
01471
01472 if( !IS_HEADER( data))
01473 {
01474
01475
01476 cvt_V792_dequeue( p_data, NULL, 1);
01477 in_org_pos= queue_ptr;
01478 break;
01479 }
01480
01481 num_word_to_read= 1;
01482 ++step;
01483 break;
01484 case 1:
01485
01486
01487 ++num_word_to_read;
01488
01489 if( !IS_EOB( data))
01490 {
01491
01492 break;
01493 }
01494
01495
01496 found_count= GET_EVENT_COUNT( data)& CVT_BOARD_EVENT_COUNT_MSK;
01497 delta_count= ( found_count- *p_event_count+ (CVT_BOARD_EVENT_COUNT_MSK+ 1))% (CVT_BOARD_EVENT_COUNT_MSK+ 1);
01498
01499
01500 if( delta_count> 0)
01501 {
01502
01503
01504 *p_out_buff_size= 0;
01505 *p_event_count= found_count;
01506 return TRUE;
01507 }
01508
01509 if( !delta_count)
01510 {
01511 if( out_buff_size< num_word_to_read)
01512 {
01513
01514 *p_out_buff_size= 0;
01515 return FALSE;
01516 }
01517
01518 if( queue_ptr>= in_org_pos)
01519 {
01520 memcpy( out_buff, p_data->m_queue+ in_org_pos, num_word_to_read*sizeof( UINT32));
01521
01522 }
01523 else
01524 {
01525
01526 long first_block_word= CVT_V792_QUEUE_SIZE_DWORD- in_org_pos;
01527 long second_block_word= num_word_to_read- first_block_word;
01528 memcpy( out_buff, p_data->m_queue+ in_org_pos, first_block_word* sizeof(UINT32));
01529 memcpy( out_buff+ first_block_word, p_data->m_queue, second_block_word* sizeof(UINT32));
01530
01531 }
01532 *p_out_buff_size= num_word_to_read;
01533
01534 return TRUE;
01535 }
01536 else
01537 {
01538
01539
01540 cvt_V792_dequeue( p_data, NULL, num_word_to_read);
01541
01542 step= 0;
01543 TRACE1( "cvt_V792_peek_event: skipped event %d\n", found_count);
01544 }
01545 break;
01546 }
01547 }
01548
01549 *p_out_buff_size= 0;
01550 return FALSE;
01551 }
01552
01554
01556 BOOL cvt_V792_inqueue( cvt_V792_data* p_data, const UINT32* in_buff, UINT32 in_buff_size)
01557 {
01558 if( !in_buff_size)
01559 return TRUE;
01560 if( cvt_V792_get_queue_free( p_data)< (long)in_buff_size)
01561 {
01562
01563 return FALSE;
01564 }
01565 if( p_data->m_queue_end+ in_buff_size< CVT_V792_QUEUE_SIZE_DWORD)
01566 {
01567 memcpy( p_data->m_queue+ p_data->m_queue_end, in_buff, in_buff_size*sizeof( UINT32));
01568 p_data->m_queue_end+= in_buff_size;
01569 }
01570 else
01571 {
01572 long first_block_word= CVT_V792_QUEUE_SIZE_DWORD- p_data->m_queue_end;
01573 long second_block_word= in_buff_size- first_block_word;
01574 memcpy( p_data->m_queue+ p_data->m_queue_end, in_buff, first_block_word* sizeof(UINT32));
01575 memcpy( p_data->m_queue, in_buff+ first_block_word, second_block_word* sizeof(UINT32));
01576 p_data->m_queue_end= second_block_word;
01577 }
01578 return TRUE;
01579 }
01580
01582
01584 BOOL cvt_V792_dequeue( cvt_V792_data* p_data, UINT32 *out_buff, UINT32 out_buff_size)
01585 {
01586 if( !out_buff_size)
01587 return TRUE;
01588 if( cvt_V792_get_queue_length( p_data)< (long)out_buff_size)
01589 {
01590
01591 return FALSE;
01592 }
01593 if( p_data->m_queue_ini+ out_buff_size< CVT_V792_QUEUE_SIZE_DWORD)
01594 {
01595 if( out_buff)
01596 {
01597 memcpy( out_buff, p_data->m_queue+ p_data->m_queue_ini, out_buff_size*sizeof( UINT32));
01598 }
01599 p_data->m_queue_ini+= out_buff_size;
01600 }
01601 else
01602 {
01603 long first_block_word= CVT_V792_QUEUE_SIZE_DWORD- p_data->m_queue_ini;
01604 long second_block_word= out_buff_size- first_block_word;
01605 if( out_buff)
01606 {
01607 memcpy( out_buff, p_data->m_queue+ p_data->m_queue_ini, first_block_word* sizeof(UINT32));
01608 memcpy( out_buff+ first_block_word, p_data->m_queue, second_block_word* sizeof(UINT32));
01609 }
01610 p_data->m_queue_ini= second_block_word;
01611 }
01612 return TRUE;
01613 }
01614
01616
01618 long cvt_V792_get_queue_free( cvt_V792_data* p_data)
01619 {
01620 return (long)CVT_V792_QUEUE_SIZE_DWORD- (( p_data->m_queue_end- p_data->m_queue_ini+ CVT_V792_QUEUE_SIZE_DWORD)%CVT_V792_QUEUE_SIZE_DWORD);
01621 }
01622
01624
01626 long cvt_V792_get_queue_length( cvt_V792_data* p_data)
01627 {
01628 return (long)(( p_data->m_queue_end- p_data->m_queue_ini+ CVT_V792_QUEUE_SIZE_DWORD)%CVT_V792_QUEUE_SIZE_DWORD);
01629 }
01630
01631 #endif // CVT_V792_USE_DATA_QUEUE
01632
01634
01636 BOOL cvt_V792_set_MCST_CBLT( cvt_V792_data* p_data, UINT8 address, MCST_CBLT_board_pos pos)
01637 {
01638 UINT16 reg_value;
01639
01640
01641 reg_value= address;
01642 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_MCST_CBLT_ADDRESS_INDEX, ®_value))
01643 {
01644 TRACE( "V792 CVT_V792_MCST_CBLT_ADDRESS write failed !\n");
01645 return FALSE;
01646 }
01647
01648
01649 switch( pos)
01650 {
01651 case MCST_CBLT_board_pos_first:
01652 reg_value= CVT_V792_MCCTRL_FIRST_BOARD_MSK;
01653 break;
01654 case MCST_CBLT_board_pos_mid:
01655 reg_value= CVT_V792_MCCTRL_MID_BOARD_MSK;
01656 break;
01657 case MCST_CBLT_board_pos_last:
01658 reg_value= CVT_V792_MCCTRL_LAST_BOARD_MSK;
01659 break;
01660 default:
01661 TRACE1( "V792 cvt_V792_set_MCST_CBLT bad position indentifier '%d'!\n", pos);
01662 return FALSE;
01663 }
01664 if( !cvt_write_reg( &p_data->m_common_data, CVT_V792_MCST_CBLT_CTRL_INDEX, ®_value))
01665 {
01666 TRACE( "V792 CVT_V792_MCST_CBLT_CTRL write failed !\n");
01667 return FALSE;
01668 }
01669
01670 return TRUE;
01671 }