cvt_V1724.c

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00001 
00002 
00010 
00011 
00013 // File includes
00015 #include <memory.h>
00016 #include <string.h>
00017 #include "cvt_V1724.h"
00018 
00020 // File local defines
00022 
00024 // Output buffer macros
00026 // TODO
00028 // Output buffer macros
00030 #define V1724_DATA_TYPE_MSK                             0xf8000000              
00032 #define V1724_GLOBAL_HEADER                             0x40000000              
00033 #define V1724_GLOBAL_TRAILER                    0x80000000              
00034 #define V1724_TDC_HEADER                                0x08000000              
00035 #define V1724_TDC_MEASURE                               0x00000000              
00036 #define V1724_TDC_ERROR                                 0x20000000              
00037 #define V1724_TDC_TRAILER                               0x18000000              
00038 #define V1724_GLOBAL_TRIGGER_TIME               0x88000000              
00039 #define V1724_FILLER                                    0xc0000000              
00041 #define IS_GLOBAL_HEADER(data)                  ((data& V1724_DATA_TYPE_MSK)== V1724_GLOBAL_HEADER)                     
00042 #define IS_GLOBAL_TRAILER(data)                 ((data& V1724_DATA_TYPE_MSK)== V1724_GLOBAL_TRAILER)            
00043 #define IS_TDC_HEADER(data)                             ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_HEADER)                        
00044 #define IS_TDC_MEASURE(data)                    ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_MEASURE)                       
00045 #define IS_TDC_ERROR(data)                              ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_ERROR)                         
00046 #define IS_TDC_TRAILER(data)                    ((data& V1724_DATA_TYPE_MSK)== V1724_TDC_TRAILER)                       
00047 #define IS_GLOBAL_TRIGGER_TIME(data)    ((data& V1724_DATA_TYPE_MSK)== V1724_GLOBAL_TRIGGER_TIME)       
00048 #define IS_FILLER(data)                                 ((data& V1724_DATA_TYPE_MSK)== V1724_FILLER)                            
00050 #define GET_EVENT_COUNT(data)                   ((UINT32)((((UINT32)data)>>5)& 0x003fffff))                                     
00055 
00056 // Static variables declaration
00057 
00058 
00060 
00065 
00066 static const cvt_reg_table CVT_V792_REG_TABLE[]=
00067 {
00068 //
00069 // Channel broadcast registers
00070         {CVT_V1724_BROAD_CH_CTRL_ADD,                   CVT_V1724_BROAD_CH_CTRL_AM,                     CVT_V1724_BROAD_CH_CTRL_DATA_SIZE},                             
00071         {CVT_V1724_BROAD_CH_SET_CTRL_ADD,               CVT_V1724_BROAD_CH_SET_CTRL_AM,         CVT_V1724_BROAD_CH_SET_CTRL_DATA_SIZE},                 
00072         {CVT_V1724_BROAD_CH_CLEAR_CTRL_ADD,             CVT_V1724_BROAD_CH_CLEAR_CTRL_AM,       CVT_V1724_BROAD_CH_CLEAR_CTRL_DATA_SIZE},               
00073         {CVT_V1724_BROAD_CH_BLKSIZE_ADD,                CVT_V1724_BROAD_CH_BLKSIZE_AM,          CVT_V1724_BROAD_CH_BLKSIZE_DATA_SIZE},                  
00074         {CVT_V1724_BROAD_CH_BLK_REM_NUM_ADD,    CVT_V1724_BROAD_CH_BLK_REM_NUM_AM,      CVT_V1724_BROAD_CH_BLK_REM_NUM_DATA_SIZE},              
00075         {CVT_V1724_BROAD_CH_READ_CONF_ADD,              CVT_V1724_BROAD_CH_READ_CONF_AM,        CVT_V1724_BROAD_CH_READ_CONF_DATA_SIZE},                
00076 //
00077 // VME registers
00078         {CVT_V1724_CONTROL_ADD,                                 CVT_V1724_CONTROL_AM,                           CVT_V1724_CONTROL_DATA_SIZE},                                   
00079         {CVT_V1724_STATUS_ADD,                                  CVT_V1724_STATUS_AM,                            CVT_V1724_STATUS_DATA_SIZE},                                    
00080         {CVT_V1724_INT_LEVEL_ADD,                               CVT_V1724_INT_LEVEL_AM,                         CVT_V1724_INT_LEVEL_DATA_SIZE},                                 
00081         {CVT_V1724_INT_VECTOR_ADD,                              CVT_V1724_INT_VECTOR_AM,                        CVT_V1724_INT_VECTOR_DATA_SIZE},                                
00082         {CVT_V1724_GEO_ADDRESS_ADD,                             CVT_V1724_GEO_ADDRESS_AM,                       CVT_V1724_GEO_ADDRESS_DATA_SIZE},                               
00083         {CVT_V1724_MCST_CBLT_ADDRESS_ADD,               CVT_V1724_MCST_CBLT_ADDRESS_AM,         CVT_V1724_MCST_CBLT_ADDRESS_DATA_SIZE},                 
00084         {CVT_V1724_MCST_CBLT_CTRL_ADD,                  CVT_V1724_MCST_CBLT_CTRL_AM,            CVT_V1724_MCST_CBLT_CTRL_DATA_SIZE},                    
00085         {CVT_V1724_SW_RESET_ADD,                                CVT_V1724_SW_RESET_AM,                          CVT_V1724_SW_RESET_DATA_SIZE},                                  
00086         {CVT_V1724_SW_CLEAR_ADD,                                CVT_V1724_SW_CLEAR_AM,                          CVT_V1724_SW_CLEAR_DATA_SIZE},                                  
00087         {CVT_V1724_SW_TRIGGER_ADD,                              CVT_V1724_SW_TRIGGER_AM,                        CVT_V1724_SW_TRIGGER_DATA_SIZE},                                
00088         {CVT_V1724_TRIGGER_ENABLE_ADD,                  CVT_V1724_TRIGGER_ENABLE_AM,            CVT_V1724_TRIGGER_ENABLE_DATA_SIZE},                    
00089         {CVT_V1724_BLT_EVENT_NUM_ADD,                   CVT_V1724_BLT_EVENT_NUM_AM,                     CVT_V1724_BLT_EVENT_NUM_DATA_SIZE},                             
00090         {CVT_V1724_FW_REV_ADD,                                  CVT_V1724_FW_REV_AM,                            CVT_V1724_FW_REV_DATA_SIZE},                                    
00091         {CVT_V1724_TEST_REG_ADD,                                CVT_V1724_TEST_REG_AM,                          CVT_V1724_TEST_REG_DATA_SIZE},                                  
00092         {CVT_V1724_FLASH_EN_ADD,                                CVT_V1724_FLASH_EN_AM,                          CVT_V1724_FLASH_EN_DATA_SIZE},                                  
00093         {CVT_V1724_FLASH_ADD,                                   CVT_V1724_FLASH_AM,                                     CVT_V1724_FLASH_DATA_SIZE},                                             
00094         {CVT_V1724_DUMMY16_ADD,                                 CVT_V1724_DUMMY16_AM,                           CVT_V1724_DUMMY16_DATA_SIZE},                                   
00095         {CVT_V1724_DUMMY32_ADD,                                 CVT_V1724_DUMMY32_AM,                           CVT_V1724_DUMMY32_DATA_SIZE},                                   
00096         {CVT_V1724_POST_TRIG_ADD,                               CVT_V1724_POST_TRIG_AM,                         CVT_V1724_POST_TRIG_DATA_SIZE},                                 
00097         {CVT_V1724_FRONT_PANEL_IO_ADD,                  CVT_V1724_FRONT_PANEL_IO_AM,            CVT_V1724_FRONT_PANEL_IO_DATA_SIZE},                    
00098         {CVT_V1724_FRONT_PANEL_IO_CTRL_ADD,             CVT_V1724_FRONT_PANEL_IO_CTRL_AM,       CVT_V1724_FRONT_PANEL_IO_CTRL_DATA_SIZE},               
00099 //
00100 // CH 0
00101         {CVT_V1724_CH0_THRESHOLD_ADD,                   CVT_V1724_CH0_THRESHOLD_AM,                     CVT_V1724_CH0_THRESHOLD_DATA_SIZE},                             
00102         {CVT_V1724_CH0_THR_SAMPLE_ADD,                  CVT_V1724_CH0_THR_SAMPLE_AM,            CVT_V1724_CH0_THR_SAMPLE_DATA_SIZE},                    
00103         {CVT_V1724_CH0_STATUS_ADD,                              CVT_V1724_CH0_STATUS_AM,                        CVT_V1724_CH0_STATUS_DATA_SIZE},                                
00104         {CVT_V1724_CH0_FW_REV_ADD,                              CVT_V1724_CH0_FW_REV_AM,                        CVT_V1724_CH0_FW_REV_DATA_SIZE},                                
00105         {CVT_V1724_CH0_READ_BLK_TRIG_ADD,               CVT_V1724_CH0_READ_BLK_TRIG_AM,         CVT_V1724_CH0_READ_BLK_TRIG_DATA_SIZE},                 
00106         {CVT_V1724_CH0_BLK_WRI_NUM_ADD,                 CVT_V1724_CH0_BLK_WRI_NUM_AM,           CVT_V1724_CH0_BLK_WRI_NUM_DATA_SIZE},                   
00107         {CVT_V1724_CH0_DAC_CONF_ADD,                    CVT_V1724_CH0_DAC_CONF_AM,                      CVT_V1724_CH0_DAC_CONF_DATA_SIZE},                              
00108         {CVT_V1724_CH0_CONF_ADD,                                CVT_V1724_CH0_CONF_AM,                          CVT_V1724_CH0_CONF_DATA_SIZE},                                  
00109         {CVT_V1724_CH0_DEBUG_ADD,                               CVT_V1724_CH0_DEBUG_AM,                         CVT_V1724_CH0_DEBUG_DATA_SIZE},                                 
00110 //
00111 // CH 1
00112         {CVT_V1724_CH1_THRESHOLD_ADD,                   CVT_V1724_CH1_THRESHOLD_AM,                     CVT_V1724_CH1_THRESHOLD_DATA_SIZE},                             
00113         {CVT_V1724_CH1_THR_SAMPLE_ADD,                  CVT_V1724_CH1_THR_SAMPLE_AM,            CVT_V1724_CH1_THR_SAMPLE_DATA_SIZE},                    
00114         {CVT_V1724_CH1_STATUS_ADD,                              CVT_V1724_CH1_STATUS_AM,                        CVT_V1724_CH1_STATUS_DATA_SIZE},                                
00115         {CVT_V1724_CH1_FW_REV_ADD,                              CVT_V1724_CH1_FW_REV_AM,                        CVT_V1724_CH1_FW_REV_DATA_SIZE},                                
00116         {CVT_V1724_CH1_READ_BLK_TRIG_ADD,               CVT_V1724_CH1_READ_BLK_TRIG_AM,         CVT_V1724_CH1_READ_BLK_TRIG_DATA_SIZE},                 
00117         {CVT_V1724_CH1_BLK_WRI_NUM_ADD,                 CVT_V1724_CH1_BLK_WRI_NUM_AM,           CVT_V1724_CH1_BLK_WRI_NUM_DATA_SIZE},                   
00118         {CVT_V1724_CH1_DAC_CONF_ADD,                    CVT_V1724_CH1_DAC_CONF_AM,                      CVT_V1724_CH1_DAC_CONF_DATA_SIZE},                              
00119         {CVT_V1724_CH1_CONF_ADD,                                CVT_V1724_CH1_CONF_AM,                          CVT_V1724_CH1_CONF_DATA_SIZE},                                  
00120         {CVT_V1724_CH1_DEBUG_ADD,                               CVT_V1724_CH1_DEBUG_AM,                         CVT_V1724_CH1_DEBUG_DATA_SIZE},                                 
00121 //
00122 // CH 2
00123         {CVT_V1724_CH2_THRESHOLD_ADD,                   CVT_V1724_CH2_THRESHOLD_AM,                     CVT_V1724_CH2_THRESHOLD_DATA_SIZE},                             
00124         {CVT_V1724_CH2_THR_SAMPLE_ADD,                  CVT_V1724_CH2_THR_SAMPLE_AM,            CVT_V1724_CH2_THR_SAMPLE_DATA_SIZE},                    
00125         {CVT_V1724_CH2_STATUS_ADD,                              CVT_V1724_CH2_STATUS_AM,                        CVT_V1724_CH2_STATUS_DATA_SIZE},                                
00126         {CVT_V1724_CH2_FW_REV_ADD,                              CVT_V1724_CH2_FW_REV_AM,                        CVT_V1724_CH2_FW_REV_DATA_SIZE},                                
00127         {CVT_V1724_CH2_READ_BLK_TRIG_ADD,               CVT_V1724_CH2_READ_BLK_TRIG_AM,         CVT_V1724_CH2_READ_BLK_TRIG_DATA_SIZE},                 
00128         {CVT_V1724_CH2_BLK_WRI_NUM_ADD,                 CVT_V1724_CH2_BLK_WRI_NUM_AM,           CVT_V1724_CH2_BLK_WRI_NUM_DATA_SIZE},                   
00129         {CVT_V1724_CH2_DAC_CONF_ADD,                    CVT_V1724_CH2_DAC_CONF_AM,                      CVT_V1724_CH2_DAC_CONF_DATA_SIZE},                              
00130         {CVT_V1724_CH2_CONF_ADD,                                CVT_V1724_CH2_CONF_AM,                          CVT_V1724_CH2_CONF_DATA_SIZE},                                  
00131         {CVT_V1724_CH2_DEBUG_ADD,                               CVT_V1724_CH2_DEBUG_AM,                         CVT_V1724_CH2_DEBUG_DATA_SIZE},                                 
00132 //
00133 // CH 3
00134         {CVT_V1724_CH3_THRESHOLD_ADD,                   CVT_V1724_CH3_THRESHOLD_AM,                     CVT_V1724_CH3_THRESHOLD_DATA_SIZE},                             
00135         {CVT_V1724_CH3_THR_SAMPLE_ADD,                  CVT_V1724_CH3_THR_SAMPLE_AM,            CVT_V1724_CH3_THR_SAMPLE_DATA_SIZE},                    
00136         {CVT_V1724_CH3_STATUS_ADD,                              CVT_V1724_CH3_STATUS_AM,                        CVT_V1724_CH3_STATUS_DATA_SIZE},                                
00137         {CVT_V1724_CH3_FW_REV_ADD,                              CVT_V1724_CH3_FW_REV_AM,                        CVT_V1724_CH3_FW_REV_DATA_SIZE},                                
00138         {CVT_V1724_CH3_READ_BLK_TRIG_ADD,               CVT_V1724_CH3_READ_BLK_TRIG_AM,         CVT_V1724_CH3_READ_BLK_TRIG_DATA_SIZE},                 
00139         {CVT_V1724_CH3_BLK_WRI_NUM_ADD,                 CVT_V1724_CH3_BLK_WRI_NUM_AM,           CVT_V1724_CH3_BLK_WRI_NUM_DATA_SIZE},                   
00140         {CVT_V1724_CH3_DAC_CONF_ADD,                    CVT_V1724_CH3_DAC_CONF_AM,                      CVT_V1724_CH3_DAC_CONF_DATA_SIZE},                              
00141         {CVT_V1724_CH3_CONF_ADD,                                CVT_V1724_CH3_CONF_AM,                          CVT_V1724_CH3_CONF_DATA_SIZE},                                  
00142         {CVT_V1724_CH3_DEBUG_ADD,                               CVT_V1724_CH3_DEBUG_AM,                         CVT_V1724_CH3_DEBUG_DATA_SIZE},                                 
00143 //
00144 // CH 4
00145         {CVT_V1724_CH4_THRESHOLD_ADD,                   CVT_V1724_CH4_THRESHOLD_AM,                     CVT_V1724_CH4_THRESHOLD_DATA_SIZE},                             
00146         {CVT_V1724_CH4_THR_SAMPLE_ADD,                  CVT_V1724_CH4_THR_SAMPLE_AM,            CVT_V1724_CH4_THR_SAMPLE_DATA_SIZE},                    
00147         {CVT_V1724_CH4_STATUS_ADD,                              CVT_V1724_CH4_STATUS_AM,                        CVT_V1724_CH4_STATUS_DATA_SIZE},                                
00148         {CVT_V1724_CH4_FW_REV_ADD,                              CVT_V1724_CH4_FW_REV_AM,                        CVT_V1724_CH4_FW_REV_DATA_SIZE},                                
00149         {CVT_V1724_CH4_READ_BLK_TRIG_ADD,               CVT_V1724_CH4_READ_BLK_TRIG_AM,         CVT_V1724_CH4_READ_BLK_TRIG_DATA_SIZE},                 
00150         {CVT_V1724_CH4_BLK_WRI_NUM_ADD,                 CVT_V1724_CH4_BLK_WRI_NUM_AM,           CVT_V1724_CH4_BLK_WRI_NUM_DATA_SIZE},                   
00151         {CVT_V1724_CH4_DAC_CONF_ADD,                    CVT_V1724_CH4_DAC_CONF_AM,                      CVT_V1724_CH4_DAC_CONF_DATA_SIZE},                              
00152         {CVT_V1724_CH4_CONF_ADD,                                CVT_V1724_CH4_CONF_AM,                          CVT_V1724_CH4_CONF_DATA_SIZE},                                  
00153         {CVT_V1724_CH4_DEBUG_ADD,                               CVT_V1724_CH4_DEBUG_AM,                         CVT_V1724_CH4_DEBUG_DATA_SIZE},                                 
00154 //
00155 // CH 5
00156         {CVT_V1724_CH5_THRESHOLD_ADD,                   CVT_V1724_CH5_THRESHOLD_AM,                     CVT_V1724_CH5_THRESHOLD_DATA_SIZE},                             
00157         {CVT_V1724_CH5_THR_SAMPLE_ADD,                  CVT_V1724_CH5_THR_SAMPLE_AM,            CVT_V1724_CH5_THR_SAMPLE_DATA_SIZE},                    
00158         {CVT_V1724_CH5_STATUS_ADD,                              CVT_V1724_CH5_STATUS_AM,                        CVT_V1724_CH5_STATUS_DATA_SIZE},                                
00159         {CVT_V1724_CH5_FW_REV_ADD,                              CVT_V1724_CH5_FW_REV_AM,                        CVT_V1724_CH5_FW_REV_DATA_SIZE},                                
00160         {CVT_V1724_CH5_READ_BLK_TRIG_ADD,               CVT_V1724_CH5_READ_BLK_TRIG_AM,         CVT_V1724_CH5_READ_BLK_TRIG_DATA_SIZE},                 
00161         {CVT_V1724_CH5_BLK_WRI_NUM_ADD,                 CVT_V1724_CH5_BLK_WRI_NUM_AM,           CVT_V1724_CH5_BLK_WRI_NUM_DATA_SIZE},                   
00162         {CVT_V1724_CH5_DAC_CONF_ADD,                    CVT_V1724_CH5_DAC_CONF_AM,                      CVT_V1724_CH5_DAC_CONF_DATA_SIZE},                              
00163         {CVT_V1724_CH5_CONF_ADD,                                CVT_V1724_CH5_CONF_AM,                          CVT_V1724_CH5_CONF_DATA_SIZE},                                  
00164         {CVT_V1724_CH5_DEBUG_ADD,                               CVT_V1724_CH5_DEBUG_AM,                         CVT_V1724_CH5_DEBUG_DATA_SIZE},                                 
00165 //
00166 // CH 6
00167         {CVT_V1724_CH6_THRESHOLD_ADD,                   CVT_V1724_CH6_THRESHOLD_AM,                     CVT_V1724_CH6_THRESHOLD_DATA_SIZE},                             
00168         {CVT_V1724_CH6_THR_SAMPLE_ADD,                  CVT_V1724_CH6_THR_SAMPLE_AM,            CVT_V1724_CH6_THR_SAMPLE_DATA_SIZE},                    
00169         {CVT_V1724_CH6_STATUS_ADD,                              CVT_V1724_CH6_STATUS_AM,                        CVT_V1724_CH6_STATUS_DATA_SIZE},                                
00170         {CVT_V1724_CH6_FW_REV_ADD,                              CVT_V1724_CH6_FW_REV_AM,                        CVT_V1724_CH6_FW_REV_DATA_SIZE},                                
00171         {CVT_V1724_CH6_READ_BLK_TRIG_ADD,               CVT_V1724_CH6_READ_BLK_TRIG_AM,         CVT_V1724_CH6_READ_BLK_TRIG_DATA_SIZE},                 
00172         {CVT_V1724_CH6_BLK_WRI_NUM_ADD,                 CVT_V1724_CH6_BLK_WRI_NUM_AM,           CVT_V1724_CH6_BLK_WRI_NUM_DATA_SIZE},                   
00173         {CVT_V1724_CH6_DAC_CONF_ADD,                    CVT_V1724_CH6_DAC_CONF_AM,                      CVT_V1724_CH6_DAC_CONF_DATA_SIZE},                              
00174         {CVT_V1724_CH6_CONF_ADD,                                CVT_V1724_CH6_CONF_AM,                          CVT_V1724_CH6_CONF_DATA_SIZE},                                  
00175         {CVT_V1724_CH6_DEBUG_ADD,                               CVT_V1724_CH6_DEBUG_AM,                         CVT_V1724_CH6_DEBUG_DATA_SIZE},                                 
00176 //
00177 // CH 7
00178         {CVT_V1724_CH7_THRESHOLD_ADD,                   CVT_V1724_CH7_THRESHOLD_AM,                     CVT_V1724_CH7_THRESHOLD_DATA_SIZE},                             
00179         {CVT_V1724_CH7_THR_SAMPLE_ADD,                  CVT_V1724_CH7_THR_SAMPLE_AM,            CVT_V1724_CH7_THR_SAMPLE_DATA_SIZE},                    
00180         {CVT_V1724_CH7_STATUS_ADD,                              CVT_V1724_CH7_STATUS_AM,                        CVT_V1724_CH7_STATUS_DATA_SIZE},                                
00181         {CVT_V1724_CH7_FW_REV_ADD,                              CVT_V1724_CH7_FW_REV_AM,                        CVT_V1724_CH7_FW_REV_DATA_SIZE},                                
00182         {CVT_V1724_CH7_READ_BLK_TRIG_ADD,               CVT_V1724_CH7_READ_BLK_TRIG_AM,         CVT_V1724_CH7_READ_BLK_TRIG_DATA_SIZE},                 
00183         {CVT_V1724_CH7_BLK_WRI_NUM_ADD,                 CVT_V1724_CH7_BLK_WRI_NUM_AM,           CVT_V1724_CH7_BLK_WRI_NUM_DATA_SIZE},                   
00184         {CVT_V1724_CH7_DAC_CONF_ADD,                    CVT_V1724_CH7_DAC_CONF_AM,                      CVT_V1724_CH7_DAC_CONF_DATA_SIZE},                              
00185         {CVT_V1724_CH7_CONF_ADD,                                CVT_V1724_CH7_CONF_AM,                          CVT_V1724_CH7_CONF_DATA_SIZE},                                  
00186         {CVT_V1724_CH7_DEBUG_ADD,                               CVT_V1724_CH7_DEBUG_AM,                         CVT_V1724_CH7_DEBUG_DATA_SIZE},                                 
00188 };
00189 
00191 // Static methods declaration
00193 
00195 // Global visible variables declaration
00197 
00199 //
00200 //     B O A R D S   H A N D L I N G
00201 //
00203 
00205 // 
00207 BOOL cvt_V1724_open( cvt_V1724_data* p_data, UINT16 base_address, long vme_handle)
00208 {
00209         memset( p_data, 0, sizeof( cvt_V1724_data));
00210 
00211         // basic data initialization
00212         if( !cvt_board_open( &p_data->m_common_data, base_address, vme_handle, CVT_V792_REG_TABLE))
00213                 return FALSE;
00214         // board specific data initialization
00215         p_data->m_common_data.set_MCST_CBLT= cvt_V1724_set_MCST_CBLT;
00216 
00217         // preallocate a suitable memory chunck for sample temporary storage
00218         p_data->m_tmp_sample_buffer_size= 16*1024;
00219         p_data->m_tmp_sample_buffer= malloc( p_data->m_tmp_sample_buffer_size* sizeof( UINT32));
00220 
00221         // HACK
00224         //if( !cvt_V1724_software_reset( p_data))
00225         //{
00226         //      TRACE( "cvt_V1724_open: error resetting board !\n");
00227         //      return FALSE;
00228         //}
00229 
00230         return TRUE;
00231 }
00232 
00234 // 
00236 BOOL cvt_V1724_close( cvt_V1724_data* p_data)
00237 {
00238         if( p_data->m_tmp_sample_buffer)
00239         {
00240                 free( p_data->m_tmp_sample_buffer);
00241                 p_data->m_tmp_sample_buffer= NULL;
00242                 p_data->m_tmp_sample_buffer_size= 0;
00243         }
00244         if( !cvt_board_close( &p_data->m_common_data))
00245                 return FALSE;
00246         return TRUE;
00247 }
00248 
00250 //
00251 //     L E V E L   0   A P I s
00252 //
00254 
00255 
00257 //
00258 //     L E V E L   1   A P I s
00259 //
00261 
00263 //
00264 //     L E V E L   2   A P I s
00265 //
00267 
00268 
00270 // 
00272 BOOL cvt_V1724_read_buffer( cvt_V1724_data* p_data, UINT8 ch_index, UINT16* p_buff, UINT32* p_buff_size)
00273 {
00274         static const UINT16 READ_BLK_TRIG[ CVT_V1724_MAX_CHANNEL]=
00275         {
00276                 CVT_V1724_CH0_READ_BLK_TRIG_INDEX,                              
00277                 CVT_V1724_CH1_READ_BLK_TRIG_INDEX,                              
00278                 CVT_V1724_CH2_READ_BLK_TRIG_INDEX,                              
00279                 CVT_V1724_CH3_READ_BLK_TRIG_INDEX,                              
00280                 CVT_V1724_CH4_READ_BLK_TRIG_INDEX,                              
00281                 CVT_V1724_CH5_READ_BLK_TRIG_INDEX,                              
00282                 CVT_V1724_CH6_READ_BLK_TRIG_INDEX,                              
00283                 CVT_V1724_CH7_READ_BLK_TRIG_INDEX,                              
00284         };
00285 
00286         static const UINT16 BLK_WRI_NUM[ CVT_V1724_MAX_CHANNEL]=
00287         {
00288                 CVT_V1724_CH0_BLK_WRI_NUM_INDEX,                                
00289                 CVT_V1724_CH1_BLK_WRI_NUM_INDEX,                                
00290                 CVT_V1724_CH2_BLK_WRI_NUM_INDEX,                                
00291                 CVT_V1724_CH3_BLK_WRI_NUM_INDEX,                                
00292                 CVT_V1724_CH4_BLK_WRI_NUM_INDEX,                                
00293                 CVT_V1724_CH5_BLK_WRI_NUM_INDEX,                                
00294                 CVT_V1724_CH6_BLK_WRI_NUM_INDEX,                                
00295                 CVT_V1724_CH7_BLK_WRI_NUM_INDEX,                                
00296         };
00297 
00298         UINT32 reg_value= 0;
00299         UINT32 num_blocks= 0;
00300 
00301         //
00302         // input param check
00303         if( ch_index>= CVT_V1724_MAX_CHANNEL)
00304         {
00305                 TRACE1( "V1724 cvt_V1724_read_buffer bad channel '%d'!\n", ch_index);
00306                 return FALSE;
00307         }
00308         //
00309         // read the number of events ready
00310         if( !cvt_read_reg( &p_data->m_common_data, BLK_WRI_NUM[ ch_index], &num_blocks))
00311         {
00312                 TRACE1( "V1724 cvt_V1724_read_buffer BLK_WRI_NUM[%d] read failed !\n", ch_index);
00313                 return FALSE;
00314         }
00315         if( !num_blocks)
00316         {
00317                 *p_buff_size= 0;
00318                 return TRUE;
00319         }
00320         //
00321         // read the number of entries ready 
00322 #define __FIFO_BLT
00323 #ifdef __FIFO_BLT
00324         {
00325                 UINT32 samples_to_read= 0;
00326                 UINT32 read= 0;
00327                 UINT32 i; 
00328                 if( !cvt_FIFO_BLT_read_reg( &p_data->m_common_data, READ_BLK_TRIG[ ch_index], &reg_value, 1* sizeof( UINT32), &read))
00329                 {
00330                         TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00331                         return FALSE;
00332                 }
00333                 if( !read)
00334                 {
00335                         *p_buff_size= 0;
00336                         return TRUE;
00337                 }
00338                 // Get the samples' number (16bit word)
00339                 samples_to_read= reg_value<< 1;
00340                 if( !samples_to_read)
00341                 {
00342                         *p_buff_size= 0;
00343                         return TRUE;
00344                 }
00345                 if( samples_to_read> 1024*1024)
00346                 {
00347                         // ????
00348                         // Remove blocks
00349                         if( !cvt_write( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_address, &num_blocks, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_am, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_data_size))
00350                         {
00351                                 TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00352                         }
00353                         return FALSE;
00354                 }
00355                 if( ( samples_to_read>>1 )> p_data->m_tmp_sample_buffer_size)
00356                 {
00357                         p_data->m_tmp_sample_buffer_size= samples_to_read>> 1;
00358                         p_data->m_tmp_sample_buffer= realloc( p_data->m_tmp_sample_buffer, p_data->m_tmp_sample_buffer_size* sizeof( UINT32));
00359                 }
00360                 if( !cvt_FIFO_BLT_read_reg( &p_data->m_common_data, READ_BLK_TRIG[ ch_index], p_data->m_tmp_sample_buffer, samples_to_read* sizeof( UINT16), &read))
00361                 {
00362                         TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00363                         return FALSE;
00364                 }
00365                 if( !read)
00366                 {
00367                         *p_buff_size= 0;
00368                         return TRUE;
00369                 }
00370                 read>>= 1;
00371                 if( *p_buff_size> read)
00372                 {
00373                         *p_buff_size= read;
00374                 }
00375                 for( i= 0; i< ((*p_buff_size)>> 1); i++)
00376                 {
00377                         p_buff[ i<< 1]= p_data->m_tmp_sample_buffer[i]& 0xffff;
00378                         p_buff[ (i<< 1)+ 1]= (p_data->m_tmp_sample_buffer[i]>> 16)& 0xffff;
00379                 }
00380         }
00381 #else
00382         if( !cvt_read( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ READ_BLK_TRIG[ ch_index]].m_address, &reg_value, cvA32_S_DATA, cvD32))
00383         {
00384                 TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00385                 return FALSE;
00386         }
00387         {
00388                 UINT32 samples_to_read= 0;
00389                 UINT32 read= 0;
00390                 UINT32 i; 
00391                 // Get the samples' number (16bit word)
00392                 samples_to_read= reg_value<< 1;
00393                 if( !samples_to_read)
00394                 {
00395                         *p_buff_size= 0;
00396                         return TRUE;
00397                 }
00398                 if( samples_to_read> 128*1024)
00399                 {
00400                         // ????
00401                         // Remove blocks
00402                         if( !cvt_write( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_address, &num_blocks, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_am, p_data->m_common_data.m_p_reg_table[ CVT_V1724_BROAD_CH_BLK_REM_NUM_INDEX].m_data_size))
00403                         {
00404                                 TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00405                         }
00406                         return FALSE;
00407                 }
00408                 if( samples_to_read> p_data->m_tmp_sample_buffer_size)
00409                 {
00410                         p_data->m_tmp_sample_buffer_size= samples_to_read;
00411                         p_data->m_tmp_sample_buffer= realloc( p_data->m_tmp_sample_buffer, p_data->m_tmp_sample_buffer_size* sizeof( UINT32));
00412                 }
00413 
00414                 if( *p_buff_size> samples_to_read)
00415                 {
00416                         *p_buff_size= samples_to_read;
00417                 }
00418                 for( i= 0; ( i< samples_to_read); i+= 2)
00419                 {
00420                         if( !cvt_read( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ READ_BLK_TRIG[ ch_index]].m_address, &reg_value, cvA32_S_DATA, cvD32))
00421                         {
00422                                 TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00423                                 return FALSE;
00424                         }
00425                         if( i>= (*p_buff_size- 1))
00426                                 continue;
00427                         p_buff[ i]= reg_value& 0xffff;
00428                         p_buff[ i+ 1]= (reg_value>> 16)& 0xffff;
00429                         //if( !cvt_read( &p_data->m_common_data, p_data->m_common_data.m_p_reg_table[ READ_BLK_TRIG[ ch_index]].m_address, &p_buff[ i], cvA32_S_DATA, cvD32))
00430                         //{
00431                         //      TRACE1( "V1724 cvt_V1724_read_buffer READ_BLK_TRIG[%d] read failed !\n", ch_index);
00432                         //      return FALSE;
00433                         //}
00434                 }
00435         }
00436 #endif
00437         return TRUE;
00438 }
00439 
00441 //
00443 BOOL cvt_V1724_set_trigger_mode( cvt_V1724_data* p_data, BOOL falling_edge_enable, BOOL trigger_in_enable, BOOL trigger_out_enable, BOOL ext_trigger_enable, BOOL sw_trigger_enable, UINT8 ch_trigger_enable_msk, BOOL trigger_overlap_enable, UINT32 post_trigger)
00444 {
00445         static const UINT16 CH_TRIGGER_MSK[ CVT_V1724_MAX_CHANNEL]=
00446         {
00447                 CVT_V1724_TRGEN_CH0_MSK,                
00448                 CVT_V1724_TRGEN_CH1_MSK,                
00449                 CVT_V1724_TRGEN_CH2_MSK,                
00450                 CVT_V1724_TRGEN_CH3_MSK,                
00451                 CVT_V1724_TRGEN_CH4_MSK,                
00452                 CVT_V1724_TRGEN_CH5_MSK,                
00453                 CVT_V1724_TRGEN_CH6_MSK,                
00454                 CVT_V1724_TRGEN_CH7_MSK,                
00455         };
00456 
00457         UINT16 set_msk16= 0;
00458         UINT16 clear_msk16= 0;
00459         UINT32 set_msk32= 0;
00460         UINT32 clear_msk32= 0;
00461 
00462         //
00463         // falling/rising edge enable ( Over/Under threshold)
00464         set_msk32|= ( falling_edge_enable)? CVT_V1724_CHCTRL_TRG_OUT_UNDER_EN_MSK: 0;
00465         clear_msk32|= ( falling_edge_enable)? 0: CVT_V1724_CHCTRL_TRG_OUT_UNDER_EN_MSK;
00466         //
00467         // trigger input enable
00468         set_msk32|= ( trigger_in_enable)? CVT_V1724_CHCTRL_TRG_IN_EN_MSK: 0;
00469         clear_msk32|= ( trigger_in_enable)? 0: CVT_V1724_CHCTRL_TRG_IN_EN_MSK;
00470         //
00471         // trigger output enable
00472         set_msk32|= ( trigger_out_enable)? CVT_V1724_CHCTRL_TRG_OUT_EN_MSK: 0;
00473         clear_msk32|= ( trigger_out_enable)? 0: CVT_V1724_CHCTRL_TRG_OUT_EN_MSK;
00474         
00475         //
00476         // setup each channel
00477         if( set_msk32)
00478         {
00479                 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_SET_CTRL_INDEX, &set_msk32))
00480                 {
00481                         TRACE( "V1724 BROADCAST CH CTRL write failed !\n");
00482                         return FALSE;
00483                 }
00484         }
00485         if( clear_msk32)
00486         {
00487                 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX, &clear_msk32))
00488                 {
00489                         TRACE( "V1724 BROADCAST CH CTRL write failed !\n");
00490                         return FALSE;
00491                 }
00492         }
00493 
00494         //
00495         // Global Channel trigger enable
00496         set_msk16|= ( ch_trigger_enable_msk)? CVT_V1724_TRGEN_ENABLE_MSK: 0;
00497 
00498         //
00499         // External trigger
00500         set_msk16|= ( ext_trigger_enable)? CVT_V1724_TRGEN_EXT_MSK: 0;
00501         clear_msk16|= ( ext_trigger_enable)? 0: CVT_V1724_TRGEN_EXT_MSK;
00502         //
00503         // Software trigger
00504         set_msk16|= ( sw_trigger_enable)? CVT_V1724_TRGEN_SW_MSK: 0;
00505         clear_msk16|= ( sw_trigger_enable)? 0: CVT_V1724_TRGEN_SW_MSK;
00506         // 
00507         // Trigger Overlap
00508         set_msk16|= ( trigger_overlap_enable)? CVT_V1724_CHCTRL_TRG_OVERLAP_MSK: 0;
00509         clear_msk16|= ( trigger_overlap_enable)? 0: CVT_V1724_CHCTRL_TRG_OVERLAP_MSK;
00510 
00511         //
00512         // Channels' trigger
00513         {
00514                 int i;
00515                 for( i= 0; i< CVT_V1724_MAX_CHANNEL ; i++, ch_trigger_enable_msk>>= 1)
00516                 {
00517                         if( ch_trigger_enable_msk& 0x01)
00518                         {
00519                                 set_msk16|= CH_TRIGGER_MSK[ i];
00520                         }
00521                         else
00522                         {
00523                                 clear_msk16|= CH_TRIGGER_MSK[ i];
00524                         }
00525                 }
00526         }
00527         //
00528         // bitmask set
00529         if( set_msk16)
00530         {
00531                 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_ENABLE_INDEX, &set_msk16))
00532                 {
00533                         TRACE( "V1724 CVT_V1724_TRIGGER_ENABLE write failed !\n");
00534                         return FALSE;
00535                 }
00536         }
00537         //
00538         // bitmask clear
00539         if( clear_msk16)
00540         {
00541                 // clear the enable bit
00542                 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_TRIGGER_ENABLE_INDEX, &clear_msk16))
00543                 {
00544                         TRACE( "V1724 CVT_V1724_TRIGGER_ENABLE write failed !\n");
00545                         return FALSE;
00546                 }
00547         }
00548 
00549         //
00550         // Post Trigger
00551         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_POST_TRIG_INDEX, &post_trigger))
00552         {
00553                 TRACE( "V1724 CVT_V1724_POST_TRIG write failed !\n");
00554                 return FALSE;
00555         }
00556         
00557         return TRUE;
00558 }
00559 
00561 //
00563 BOOL cvt_V1724_set_acquisition_mode( cvt_V1724_data* p_data, BOOL sample_enable, CVT_V1724_CH_BLKSIZE block_size)
00564 {
00565         UINT32 set_msk= 0;
00566         UINT32 clear_msk= 0;
00567 
00568         //
00569         // parameter checking
00570         switch( block_size)
00571         {
00572         case CVT_V1724_CHBKSZ_512:                              
00573         case CVT_V1724_CHBKSZ_1K:                               
00574         case CVT_V1724_CHBKSZ_2K:                               
00575         case CVT_V1724_CHBKSZ_4K:                               
00576         case CVT_V1724_CHBKSZ_8K:                               
00577         case CVT_V1724_CHBKSZ_16K:                              
00578         case CVT_V1724_CHBKSZ_32K:                              
00579         case CVT_V1724_CHBKSZ_64K:                              
00580         case CVT_V1724_CHBKSZ_128K:                             
00581         case CVT_V1724_CHBKSZ_256K:                             
00582         case CVT_V1724_CHBKSZ_512K:                             
00583                 break;
00584         default:
00585                 TRACE1( "V1724 Bad block size '%d'!\n", block_size);
00586                 return FALSE;
00587         }
00588         //
00589         // Sample enable
00590         set_msk|= ( sample_enable)? CVT_V1724_CHCTRL_SAMPLE_ACQ_MSK: 0;
00591         clear_msk|= ( sample_enable)? 0: CVT_V1724_CHCTRL_SAMPLE_ACQ_MSK;
00592         
00593         //
00594         // setup each channel
00595         if( set_msk)
00596         {
00597                 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_SET_CTRL_INDEX, &set_msk))
00598                 {
00599                         TRACE( "V1724 CH SET CONTROL write failed !\n");
00600                         return FALSE;
00601                 }
00602         }
00603         if( clear_msk)
00604         {
00605                 if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_CLEAR_CTRL_INDEX, &clear_msk))
00606                 {
00607                         TRACE( "V1724 CH CLEAR CONTROL write failed !\n");
00608                         return FALSE;
00609                 }               
00610         }
00611         //
00612         // Block size   
00613         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BROAD_CH_BLKSIZE_INDEX, &block_size))
00614         {
00615                 TRACE( "V1724 CH BLOCK SIZE write failed !\n");
00616                 return FALSE;
00617         }               
00618         return TRUE;
00619 }
00620 
00622 //
00624 BOOL cvt_V1724_set_dither_enable( cvt_V1724_data* p_data, UINT8 ch_msk, BOOL dither_value)
00625 {
00626         static const UINT16 CH_CONF[ CVT_V1724_MAX_CHANNEL]=
00627         {
00628                 CVT_V1724_CH0_CONF_INDEX,                       
00629                 CVT_V1724_CH1_CONF_INDEX,                       
00630                 CVT_V1724_CH2_CONF_INDEX,                       
00631                 CVT_V1724_CH3_CONF_INDEX,                       
00632                 CVT_V1724_CH4_CONF_INDEX,                       
00633                 CVT_V1724_CH5_CONF_INDEX,                       
00634                 CVT_V1724_CH6_CONF_INDEX,                       
00635                 CVT_V1724_CH7_CONF_INDEX,                       
00636         };
00637         UINT16 set_msk= 0;
00638         //
00639         // Dither enable
00640         set_msk|= CVT_V1724_CHCONF_DITHER_MSK;
00641 
00642         if( dither_value)
00643         {
00644                 int i;
00645                 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
00646                 {
00647                         if( !(ch_msk& 0x01))
00648                                 continue;
00649                         if( !cvt_set_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk))
00650                         {
00651                                 TRACE( "V1724 CH CONF write failed !\n");
00652                                 return FALSE;
00653                         }
00654                 }
00655         }
00656         else
00657         {
00658                 int i;
00659                 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
00660                 {
00661                         if( !(ch_msk& 0x01))
00662                                 continue;
00663                         if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CH_CONF[ i], &set_msk))
00664                         {
00665                                 TRACE( "V1724 CH CONF write failed !\n");
00666                                 return FALSE;
00667                         }
00668                 }
00669         }
00670         return TRUE;
00671 }
00672 
00674 //
00676 BOOL cvt_V1724_set_interrupt( cvt_V1724_data* p_data, UINT8 level, UINT8 vector, UINT8 event_number)
00677 {
00678         UINT16 reg_value;
00679         //
00680         // interrupt level
00681         reg_value= level& 0x07;
00682         if( level!= reg_value)
00683         {
00684                 TRACE( "V1724 bad interrupt level !\n");
00685                 return FALSE;
00686         }
00687         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_INT_LEVEL_INDEX, &reg_value))
00688         {
00689                 TRACE( "V1724 CVT_V1724_INT_LEVEL write failed !\n");
00690                 return FALSE;
00691         }
00692         //
00693         // interrupt vector
00694         reg_value= vector;
00695         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_INT_VECTOR_INDEX, &reg_value))
00696         {
00697                 TRACE( "V1724 CVT_V1724_INT_VECTOR write failed !\n");
00698                 return FALSE;
00699         }
00700 /* TODO: not jet implemented onto board fpga
00701         //
00702         // event number (event trigger register)
00703         reg_value= event_number& 0x1f;
00704         if( event_number!= reg_value)
00705         {
00706                 TRACE( "V1724 bad interrupt event number !\n");
00707                 return FALSE;
00708         }
00709         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_EVENT_TRG_INDEX, &reg_value))
00710         {
00711                 TRACE( "V1724 CVT_V1724_EVENT_TRG write failed !\n");
00712                 return FALSE;
00713         }
00714 */
00715         return TRUE;
00716 }
00717 
00719 //
00721 BOOL cvt_V1724_set_readout_mode( cvt_V1724_data* p_data, BOOL enable_bus_error, UINT16 BLT_event_number)
00722 {
00723         UINT16 set_msk= 0;
00724         UINT16 clear_msk= 0;
00725         
00726         //
00727         // Bus error
00728         set_msk|= ( enable_bus_error)? CVT_V1724_CTRL_BERR_ENABLE_MSK: 0;
00729         clear_msk|= ( enable_bus_error)? 0: CVT_V1724_CTRL_BERR_ENABLE_MSK;
00730         
00731         //
00732         // bitmask set
00733         if( set_msk)
00734         {
00735                 if( !cvt_set_bitmask_reg( &p_data->m_common_data, CVT_V1724_CONTROL_INDEX, &set_msk))
00736                 {
00737                         TRACE( "V1724 CVT_V1724_CONTROL write failed !\n");
00738                         return FALSE;
00739                 }
00740         }
00741         //
00742         // bitmask clear
00743         if( clear_msk)
00744         {
00745                 // clear the enable bit
00746                 if( !cvt_clear_bitmask_reg( &p_data->m_common_data, CVT_V1724_CONTROL_INDEX, &clear_msk))
00747                 {
00748                         TRACE( "V1724 CVT_V1724_CONTROL write failed !\n");
00749                         return FALSE;
00750                 }
00751         }
00752 
00753         // 
00754         // BLT event number
00755         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_BLT_EVENT_NUM_INDEX, &BLT_event_number))
00756         {
00757                 TRACE( "V1724 CVT_V1724_BLT_EVENT_NUM write failed !\n");
00758                 return FALSE;
00759         }
00760 
00761         return TRUE;
00762 }
00763 
00765 // 
00767 BOOL cvt_V1724_software_reset( cvt_V1724_data* p_data)
00768 {
00769         //
00770         // Write CVT_V1724_SW_RESET register
00771         UINT16 reg_value= 0;
00772         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_RESET_INDEX, &reg_value))
00773         {
00774                 TRACE( "V1724 CVT_V1724_SW_RESET write failed !\n");
00775                 return FALSE;
00776         }
00777         return TRUE;
00778 }
00779 
00781 //
00783 BOOL cvt_V1724_data_clear( cvt_V1724_data* p_data)
00784 {
00785         //
00786         // Write CVT_V1724_SW_RESET register
00787         UINT16 reg_value= 0;
00788         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_CLEAR_INDEX, &reg_value))
00789         {
00790                 TRACE( "V1724 CVT_V1724_CLEAR_RESET write failed !\n");
00791                 return FALSE;
00792         }
00793         return TRUE;
00794 }
00795 
00797 //
00799 BOOL cvt_V1724_set_channel_offset( cvt_V1724_data* p_data, UINT8 ch_msk, UINT16 offset_value)
00800 {
00801         static const UINT16 CH_DAC_CONF[ CVT_V1724_MAX_CHANNEL]=
00802         {
00803                 CVT_V1724_CH0_DAC_CONF_INDEX,           
00804                 CVT_V1724_CH1_DAC_CONF_INDEX,           
00805                 CVT_V1724_CH2_DAC_CONF_INDEX,           
00806                 CVT_V1724_CH3_DAC_CONF_INDEX,           
00807                 CVT_V1724_CH4_DAC_CONF_INDEX,           
00808                 CVT_V1724_CH5_DAC_CONF_INDEX,           
00809                 CVT_V1724_CH6_DAC_CONF_INDEX,           
00810                 CVT_V1724_CH7_DAC_CONF_INDEX,           
00811         };
00812         UINT32 reg_value_A= 0, reg_value_B= 0;
00813         //
00814         // Channel offset
00815 
00816         //
00817         // Data for DAC A ( even channels)
00818         CVT_V1724_SET_CH_DAC_CONF( reg_value_A, offset_value);
00819         reg_value_A|= CVT_V1724_CHDAC_SET_A_MSK;
00820         //
00821         // Data for DAC B ( odd channels)
00822         CVT_V1724_SET_CH_DAC_CONF( reg_value_B, offset_value);
00823         reg_value_B|= CVT_V1724_CHDAC_SET_B_MSK;
00824         
00825         //
00826         // setup each channel
00827         {
00828                 int i;
00829                 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& ch_msk; i++, ch_msk>>= 1)
00830                 {
00831                         if( ch_msk& 0x01)
00832                         {
00833                                 //
00834                                 // Wait for DAC !busy
00835                                 BOOL trash;
00836                                 BOOL is_dac_busy= TRUE;
00837                                 while( is_dac_busy)
00838                                 {
00839                                         // HACK insert timeout here
00840 
00841                                         if( !cvt_V1724_get_channel_status( p_data, i, &is_dac_busy, &trash, &trash, &trash))
00842                                         {
00843                                                 TRACE( "V1724 set channel offset failed !\n");
00844                                                 return FALSE;
00845                                         }
00846                                 }
00847                                 if( !cvt_write_reg( &p_data->m_common_data, CH_DAC_CONF[ i], ( i& 0x01)? &reg_value_B: &reg_value_A))
00848                                 {
00849                                         TRACE( "V1724 CH DAC CONF write failed !\n");
00850                                         return FALSE;
00851                                 }
00852                         }
00853                 }
00854         }
00855 
00856         return TRUE;
00857 }
00858 
00860 //
00862 BOOL cvt_V1724_set_channel_trigger( cvt_V1724_data* p_data, UINT8 ch_msk, UINT32 trigger_threshold, UINT32 threshold_samples)
00863 {
00864         static const UINT16 CH_TRG_THR[ CVT_V1724_MAX_CHANNEL]=
00865         {
00866                 CVT_V1724_CH0_THRESHOLD_INDEX,                                  
00867                 CVT_V1724_CH1_THRESHOLD_INDEX,                                  
00868                 CVT_V1724_CH2_THRESHOLD_INDEX,                                  
00869                 CVT_V1724_CH3_THRESHOLD_INDEX,                                  
00870                 CVT_V1724_CH4_THRESHOLD_INDEX,                                  
00871                 CVT_V1724_CH5_THRESHOLD_INDEX,                                  
00872                 CVT_V1724_CH6_THRESHOLD_INDEX,                                  
00873                 CVT_V1724_CH7_THRESHOLD_INDEX,                                  
00874         };
00875 
00876         static const UINT16 CH_TRG_THR_SAMPLE[ CVT_V1724_MAX_CHANNEL]=
00877         {
00878                 CVT_V1724_CH0_THR_SAMPLE_INDEX,                         
00879                 CVT_V1724_CH1_THR_SAMPLE_INDEX,                         
00880                 CVT_V1724_CH2_THR_SAMPLE_INDEX,                         
00881                 CVT_V1724_CH3_THR_SAMPLE_INDEX,                         
00882                 CVT_V1724_CH4_THR_SAMPLE_INDEX,                         
00883                 CVT_V1724_CH5_THR_SAMPLE_INDEX,                         
00884                 CVT_V1724_CH6_THR_SAMPLE_INDEX,                         
00885                 CVT_V1724_CH7_THR_SAMPLE_INDEX,                         
00886         };
00887 
00888         //
00889         // trigger threshold
00890         {
00891                 int i;
00892                 UINT8 tmp_msk= ch_msk;
00893                 UINT32 reg_value= trigger_threshold;
00894                 for( i= 0; (i< CVT_V1724_MAX_CHANNEL )&& tmp_msk; i++, tmp_msk>>= 1)
00895                 {
00896                         if( tmp_msk& 0x01)
00897                         {
00898                                 if( !cvt_write_reg( &p_data->m_common_data, CH_TRG_THR[ i], &reg_value))
00899                                 {
00900                                         TRACE( "V1724 CH TRIGGER THRESHOLD write failed !\n");
00901                                         return FALSE;
00902                                 }
00903                         }
00904                 }
00905         }
00906 
00907         //
00908         // trigger threshold samples
00909         {
00910                 int i;
00911                 UINT8 tmp_msk= ch_msk;
00912                 UINT32 reg_value= threshold_samples;
00913                 for( i= 0; (i< CVT_V1724_MAX_CHANNEL)&& tmp_msk; i++, tmp_msk>>= 1)
00914                 {
00915                         if( tmp_msk& 0x01)
00916                         {
00917                                 if( !cvt_write_reg( &p_data->m_common_data, CH_TRG_THR_SAMPLE[ i], &reg_value))
00918                                 {
00919                                         TRACE( "V1724 CH TRIGGER THRESHOLD SAMPLES write failed !\n");
00920                                         return FALSE;
00921                                 }
00922                         }
00923                 }
00924         }
00925         return TRUE;
00926 }
00927 
00929 //
00931 BOOL cvt_V1724_software_trigger( cvt_V1724_data* p_data)
00932 {
00933         UINT16 reg_value;
00934         //
00935         // software trigger
00936         reg_value= 1;
00937         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_SW_TRIGGER_INDEX, &reg_value))
00938         {
00939                 TRACE( "V1724 CVT_V1724_SW_TRIGGER write failed !\n");
00940                 return FALSE;
00941         }
00942         return TRUE;
00943 }
00944 
00945 
00947 //
00949 BOOL cvt_V1724_get_channel_status( cvt_V1724_data* p_data, UINT8 ch_index, BOOL *p_is_dac_busy, BOOL *p_is_fifo_full, BOOL *p_is_fifo_empty, BOOL *p_is_block_remove_ok)
00950 {
00951         static const UINT16 CH_STATUS[ CVT_V1724_MAX_CHANNEL]=
00952         {
00953                 CVT_V1724_CH0_STATUS_INDEX,                                             
00954                 CVT_V1724_CH1_STATUS_INDEX,                                             
00955                 CVT_V1724_CH2_STATUS_INDEX,                                             
00956                 CVT_V1724_CH3_STATUS_INDEX,                                             
00957                 CVT_V1724_CH4_STATUS_INDEX,                                             
00958                 CVT_V1724_CH5_STATUS_INDEX,                                             
00959                 CVT_V1724_CH6_STATUS_INDEX,                                             
00960                 CVT_V1724_CH7_STATUS_INDEX,                                             
00961         };
00962 
00963         UINT32 reg_value= 0;
00964 
00965         //
00966         // input param check
00967         if( ch_index>= CVT_V1724_MAX_CHANNEL)
00968         {
00969                 TRACE1( "V1724 cvt_V1724_get_channel_status bad channel '%d'!\n", ch_index);
00970                 return FALSE;
00971         }
00972         //
00973         // read channel status register 1
00974         if( !cvt_read_reg( &p_data->m_common_data, CH_STATUS[ ch_index], &reg_value))
00975         {
00976                 TRACE1( "V1724 CH_STATUS[%d] read failed !\n", ch_index);
00977                 return FALSE;
00978         }
00979         *p_is_dac_busy= ( reg_value& CVT_V1724_CHSTS_DAC_BUSY_MSK)? TRUE: FALSE;
00980         *p_is_fifo_full= ( reg_value& CVT_V1724_CHSTS_FIFO_FULL_MSK)? TRUE: FALSE;
00981         *p_is_fifo_empty= ( reg_value& CVT_V1724_CHSTS_FIFO_EMPTY_MSK)? TRUE: FALSE;
00982         *p_is_block_remove_ok= ( reg_value& CVT_V1724_CHSTS_BLOCK_REM_OK_MSK)? TRUE: FALSE;
00983 
00984         return TRUE;
00985 }
00986 
00988 
00998 
00999 BOOL cvt_V1724_get_system_info( cvt_V1724_data* p_data, UINT16 *p_firmware_rev, UINT16 *p_serial_number)
01000 {
01001         UINT16 reg_value= 0;
01002         //
01003         // Firmware revision register
01004         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_FW_REV_INDEX, &reg_value))
01005         {
01006                 TRACE( "V1724 CVT_V1724_FW_REV read failed !\n");
01007                 return FALSE;
01008         }
01009         *p_firmware_rev= reg_value;
01010 /*
01011         //
01012         // Serial number
01013         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_SERIAL_LSB_INDEX, &reg_value))
01014         {
01015                 TRACE( "V1724 CVT_V1724_ROM_SERIAL_LSB read failed !\n");
01016                 return FALSE;
01017         }
01018         *p_serial_number= reg_value& 0x00ff;
01019         if( !cvt_read_reg( &p_data->m_common_data, CVT_V1724_ROM_SERIAL_MSB_INDEX, &reg_value))
01020         {
01021                 TRACE( "V1724 CVT_V1724_ROM_SERIAL_MSB read failed !\n");
01022                 return FALSE;
01023         }
01024         *p_serial_number|= (reg_value& 0x00ff)<< 8;
01025 */
01026         *p_serial_number= 0;
01027 
01028         return TRUE;
01029 }
01030 
01032 //
01034 BOOL cvt_V1724_set_MCST_CBLT( cvt_V1724_data* p_data, UINT8 address, MCST_CBLT_board_pos pos)
01035 {
01036         UINT16 reg_value;
01037         //
01038         // MCST/CBLT address register
01039         reg_value= address;
01040         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_MCST_CBLT_ADDRESS_INDEX, &reg_value))
01041         {
01042                 TRACE( "V1724 CVT_V1724_MCST_CBLT_ADDRESS write failed !\n");
01043                 return FALSE;
01044         }
01045         //
01046         // MCST/CBLT control register
01047         switch( pos)
01048         {
01049         case MCST_CBLT_board_pos_first:
01050                 reg_value= CVT_V1724_MCCTRL_FIRST_BOARD_MSK;
01051                 break;
01052         case MCST_CBLT_board_pos_mid:
01053                 reg_value= CVT_V1724_MCCTRL_MID_BOARD_MSK;
01054                 break;
01055         case MCST_CBLT_board_pos_last:
01056                 reg_value= CVT_V1724_MCCTRL_LAST_BOARD_MSK;
01057                 break;
01058         default:
01059                 TRACE1( "V1724 cvt_V1724_set_MCST_CBLT bad position indentifier '%d'!\n", pos);
01060                 return FALSE;
01061         }
01062         if( !cvt_write_reg( &p_data->m_common_data, CVT_V1724_MCST_CBLT_CTRL_INDEX, &reg_value))
01063         {
01064                 TRACE( "V1724 CVT_V1724_MCST_CBLT_CTRL write failed !\n");
01065                 return FALSE;
01066         }
01067 
01068         return TRUE;
01069 }

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